High speed digital signal processor for signed digit numbers

Details High speed digital signal processor for signed digit numbers High speed digital signal processor for signed digit numbers

1989-01-27

1991-01-15

Shaw, Dale M.

Boots, shoes, and leggings

3647505, 364754, G06F 700, G06F 1500

Patent

active

049858610

ABSTRACT:
For improvement in processing speed, a high-speed digital signal processor has a feedback loop from a register which stores the calculating result produced by a Signed Digit (SD) arithmetic unit to one of the input ports of the SD arithmetic unit. The SD arithmetic unit executes an arithmetic operation on an input digital signal and the arithmetic result is formed of both signed digit numbers without the need to convert the calculation result represented by an SD number into a binary number.

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Maholick et al., "Ternary Full Adder", IBM Technical Disclosure Bulletin, vol. 18, #4, pp. 1145-1146, Sep., 1975.
Kuninobu et al., "Design of a High Speed MOS Multiplier and Divider Using Redundant Binary Representation", Proc. 8th Symposium on Computer Arithmetic, pp. 80-86, May, 1987.
Harata et al., "High Speed Multiplier Using a Redundant Binary Adder Tree", IEEE International Conf. on Computer Design, pp. 165-170, 1984.

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