High speed digital signal processor capable of achieving realtim

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364754, G06F 752

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active

049455060

ABSTRACT:
A digital signal processor for computing a vector product between a column vector input signal including a plurality of data items (x0, x1, x2, . . . , x7) and a matrix including a predetermined number of coefficient data items so as to produce a column vector output signal including a plurality of data items (y0, y1, y2, . . . , y7). In a first cycle, the leading data x0 of the column vector input signal is stored in a first store unit (Rin), whereas during this period of time, in a second cycle shorter in time than the first cycle, the data items (c0, c1, c2, . . . , c7) in the row direction constituting a first portion of the matrix are sequentially read out such that both data items are multiplied, thereby storing the multiplication results in an accumulator. A similar data processing is repeatedly executed so as to obtain, based on the outputs from the accumulator, a column vector output signal constituted by the plurality of data items (y0, y1, y2, . . . , y7).

REFERENCES:
patent: 4760517 (1988-07-01), Miller et al.
patent: 4777614 (1988-10-01), Ward
patent: 4787057 (1988-11-01), Hammond
patent: 4811268 (1989-03-01), Nishitani et al.
LSI Handbook, OHM-Sha Ltd., Nov. 30, 1984, pp. 567-607.
Technical Review of the Institute of Electronic and Communication Engineers of Japan, IE85-4, 1985, pp. 23-30.

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