High speed digital signal processor

Details High speed digital signal processor High speed digital signal processor

1998-08-28

2001-03-27

Malzahn, David H. (Department: 2121)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S551000

Reexamination Certificate

active

06209017

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a digital signal processor(DSP) for processing various digital signals depending upon any programs.
2. Description of the Prior Art
Conventionally, the DSP can employ any one of a floating-point arithmetic and a fixed-point arithmetic. The floating-point arithmetic has a disadvantage in that it provides more accurate result than, but costs considerably more than the fixed-point arithmetic. Accordingly, most DSPs employ the fixed-point arithmetic. In order to prevent the error generation, the DSP of fixed-point arithmetic system having a typical N bit wordlength makes use of an arithmetic logic unit(ALU) having a ‘8+2N’ bit wordlength and an accumulating register. Herein, ‘8’ refers to the extra bits for overflow guarding commonly used. Because all the ALU and accumulating register is lengthened at least twice more than the data wordlength N, an operation amount in the DSP is not only increased, but also a response speed of the DSP is reduced. Also, there are DSPs without the extra bits.
Actually, first and second data
10
and
12
having each an integer part and a fractional part and an N bit wordlength, as shown in
FIG. 1
, is read out of memory(not shown), and multiplied by means of a multiplier
14
. A multiplied data having at most 2N bit length is generated at the multiplier
14
. Such a multiplied data is temporarily stored in a product register
16
. The multiplied data stored in the product register
16
is moved toward an accumulating register
20
through an ALU(
18
) in a state in which it is shifted by the bit number corresponding to the integer parts of the first and second data. The data removed to the accumulating register
20
has a new value in the case of data being operated by the ALU. An overflow can be generated in the data which is stored in the accumulating register
20
. To this end, a serious error is generated in the data of the accumulating register
20
. In order to reduce the serious error caused by the overflow, DSPs in TMS320C5x series developed by Texas Instrument Co. Ltd., have a saturation operating function instead of having the overflow prevention bits. On the other hand, DSPs of DSP5600x series developed by Motorola Corp. add 8 extra bits to the accumulating register
20
for the purpose of overflow guarding as shown in FIG.
1
. In this case, the ALU and the accumulating register
20
included in the DSP have a ‘8+2N’ bit length. When the 8 bit of extra bits are applied to the DSP having a 24 bit wordlength, each of the ALU and the accumulating register
20
included in the DSP has a 56 bit length; while when the 8 bit of extra bits are applied to the DSP having a 20 bit wordlength, each of them has a 46 bit length. The ALU and accumulating register, having a wordlength of more than 48 bits causes the die size of the DSP chip as well as the manufacturing cost thereof to be increased. Also, the operating speed of the DSP becomes slow because a propagation delay amount, in the ALU having a large wordlength, is great.
The data stored in the accumulating register
20
, hereinafter referred to as “accumulated data”, is saturated prior to being transferred to the memory. By this saturation process, the accumulated data is changed into a third data
22
having a bit length equal to the first and second data
10
and
12
. Prior to performing such a saturation process, some DSP allows a rounding operation to be performed. For example, the DSP of Motorola corp. converts the ‘8+2N’ bit data stored in the accumulator
20
into a ‘8+N’ bit data under a command word ‘rnd’. The saturation process to be performed after that time, changes the rounded data into an N bit of third data
22
.
The DSPs using the method as described above, additionally wastes one command word or one clock period for the rounding operation. Due to this, clock periods additionally wasted become great when the rounding operation is involved in a code segment including a looping or a block repeating. As a result, an operation amount performed by the DSP increases.
Furthermore, the DSP in TMS320C5x model of Texas Instrument Co. Ltd. shift the data to be calculated with the ALU to the left by 0 to 16 bits using a pre-scaling shifter arranged at the previous stage of the ALU. In this case, the shift operation from the ‘
0
’ numbered bit to the ‘
15
’ numbered bit is usually used for scaling the data, but the shift operation to the ‘
16
’ numbered bit is used when performing a fixed-point arithmetic rather than an integer arithmetic. This results from a fact that the 16 bit data read out of the memory must be arrayed to high order bits of the 32 bit accumulating register. The shift operation from the ‘
0
’ numbered bit to the ‘
15
’ numbered bit for scaling the data may or may not be used effectively depending upon a given algorithm, particularly upon a algorithm coding method. When performing an algorithm implemented with a code in which the pre-scaling is not used effectively, the pre-scaling shifter causes the die size of the DSP chip to be enlarged and the propagation delay amount to be increased, without any useful advantage. For example, the pre-scaling shifter included in the DSP of Motorola Corp. shift the data, by one bit, to the left or the right. Instead, the DSP of Motorola Corp. provides different multiplying command words for the fixed-point arithmetic and the integer arithmetic, thereby absorbing an operation which shifts the data, by 16 bits, to the left in the TMS320C5x of Texas Instrument Co. Ltd.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a digital signal processor that includes an ALU and an accumulating register having a short wordlength.
Further object of the present invention is to provide a digital signal processor that does not waste an additional clock period at the time of rounding of data.
Another object of the present invention is to provide a digital signal processor that is capable of effectively performing an integer arithmetic and/or a fixed-point arithmetic.
Still another object of the present invention is to provide a digital signal processor that is capable of performing an operation including a data scaling in a high speed.
Still another object of the present invention is to provide a digital signal processor that can eliminate a rounding procedure of data.
In order to achieve these and other objects of the invention, a digital signal processor according to an aspect of the present invention includes data input means for receiving a N-bit data; rounding bit adding means for adding r-bit rounding bits to the N-bit data from the data input means, wherein r is smaller than N; guard bit adding means for adding g-bit guard bits to the high-order bits of the data from the rounding bit adding means; means for operating the data from the guard bit adding means; and rounding/saturation means for making a rounding process, a saturation process and a combined process including the rounding and saturation processes for the data from the operating means.
A digital signal processor according to still another aspect of the present invention includes data input means for receiving an N-bit data; an alignment unit for aligning the N-bit data from the data input means to the left of (N+r)-bit bus; means for operating the data from the (N+r)-bit bus; and deriving means for deriving only the high-order N bits from the data from the operating means.
A digital signal processor according to still another aspect of the present invention includes input means for receiving an N-bit data; means for operating the data from the input means and a data from a feedback loop; a memory connected to the feedback loop for temporarily storing the data from the operating means; means for scaling the data from the input means; and selecting means for selectively transferring the data from the scaling means and the data from the operating means to the memory.
A digital signal processor according to still another aspect of the prese

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