High-speed digital PLL device

Details High-speed digital PLL device High-speed digital PLL device

1990-09-06

1991-07-30

Mis, David

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

331 34, 375120, H03L 706, H03L 7081

Patent

active

050362976

ABSTRACT:
In a device for producing a signal in synchronism with the phase of an input signal, a tapped delay timer produces a plurality of signals which have phases different from each other, a selection circuit selectively outputs the output signals of the tapped delay circuit, a frequency divider frequency-divides the output signal of the selection signal, a phase comparator compares the phases of the input digital signal and the output signal of the frequency divider, and a control circuit controls the selection circuit in accordance with the output of the phase comparator, so as to make the phase of the output signal of the frequency-divider to coincide with the input digital signal. A low-pass filter is provided to remove the hazard that is generated in the selection circuit. A waveform shaping circuit is provided to shape the waveform of the output signal of the low-pass filter into rectangular waveform.

REFERENCES:
patent: 3509471 (1970-04-01), Puente
patent: 4336505 (1982-06-01), Meyer
patent: 4617679 (1986-10-01), Brooks
patent: 4873491 (1989-10-01), Wilkins
patent: 4912433 (1990-03-01), Motegi et al.
patent: 4937846 (1990-06-01), Malka et al.
Masayasu Hata, et al., "How to Use PLL-IC", Akiba Shuppan, (1986) p. 139.

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