High speed digital parallel multiplier

Details High speed digital parallel multiplier High speed digital parallel multiplier

1994-12-05

1995-11-07

Envall, Jr., Roy N.

Boots, shoes, and leggings

364760, G06F 752

Patent

active

054652260

ABSTRACT:
A plurality of multiplicand bit transmission lines and a plurality of multiplier bit transmission lines or their decoding signal transmission lines are arranged in a two-dimensional plane, and partial product generators are arranged at their intersections. A plurality of rows of first multi-input adders are arranged at predetermined numbers of rows, and at least one row of second multi-input adders are arranged at predetermined numbers of the first multi-input adders. A basic cell is formed by a predetermined number of partial product generators and one first multi-input adder, and the basic cells are repetitively arranged to obtain a rectangular configuration.

REFERENCES:
patent: 4168530 (1979-09-01), Gajski et al.
patent: 4545028 (1985-10-01), Ware
patent: 4745570 (1988-05-01), Diedrich et al.
patent: 4748584 (1988-05-01), Noda
patent: 4752905 (1988-06-01), Nakagawa et al.
The Westin Copley Place Hotel, Proceedings of the IEEE 1990 Custom Integrated Circuits Conference, May 13-16, 1990, Boston, Massachusetts.
T. Sato et al., A Regularly Structured 54-Bit Modified-Wallace Tree Multiplier, Aug. 20-22, 1991, Edinburgh, Scotland.

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