Pulse or digital communications – Transmitters
Reexamination Certificate
2000-02-25
2001-06-12
Chin, Stephen (Department: 2734)
Pulse or digital communications
Transmitters
C370S522000, C375S354000
Reexamination Certificate
active
06246726
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the transmission and receipt of digital data. More particularly, the invention concerns the exchange of a digital data input stream where a transmitter sends the digital data input stream to a receiver, the receiver sequentially dividing the stream into different interleaved substreams and later combining the substreams to reconstruct the original digital data input stream.
2. Description of the Related Art
Many electronic machines, such as computers, are made up of multiple different subcomponents. These subcomponents are often interconnected by a hardwired electrical connection such as a bus, etc. In many cases, however, some distance separates the subcomponents, preventing any convenient permanent electrical connection. Interconnected subcomponents may be separated by a few feet or even dozens of yards. Here, it is common to interconnect the remotely coupled subsystems using wires, cables, or another signal transmitting medium. These couplings are called “cable connections” in this application. Cable interconnections between subcomponents are crucial to the operation of these subcomponents as well as the overall system.
The transmission of data over cable interconnections is frequently coordinated with a clock signal, such as a square wave signal. As shown in
FIG. 1
, data transmissions are often broken down into multiple parts
100
-
105
, such as bytes. Transmission and/or receipt of the individual bytes is coordinated by a clock signal. In the example of
FIG. 1
, the timing of each byte
100
-
105
has a one-to-one timing relationship with a rising edge of a clock signal
110
.
Generally, it is desirable to transmit data as fast as possible to avoid delaying the operation of the subcomponents or the ultimate application program. Consequently, design engineers are constantly seeking faster and faster data rates. And, faster data rates require faster clock signals to synchronize transmission of the data, since each data byte requires a separate rising edge of the clock signal.
A number of problems can arise when a clock signal becomes too fast, however. For example, sufficiently high speed clock signals often have poorly defined edges, resulting in false clock cycle transitions. False transitions in a clocking signal may ultimately corrupt the data whose transmission depends upon the clock signal's accuracy. Therefore, the maximum data transmission speed is often limited by the maximum clock signal frequency.
SUMMARY OF THE INVENTION
Broadly, the present invention involves the exchange of a digital data input stream, where a transmitter sends the digital data input stream to a receiver, and the receiver sequentially divides the stream into different interleaved substreams and later combines the substreams to reconstruct the original digital data input stream.
More particularly, the original digital data input stream is first received by a communications module. The original digital data input stream includes multiple subgroups of data, such as bytes. Each subgroup is stored in a selected buffer of the communications module. Buffers are selected in a predetermined order of rotation to store sequentially received subgroups. Thus, each buffer receives subgroups in a defined order. Later, each buffer outputs its stored subgroups in the same order as received. A data assembler assembles the subgroups output by the various buffers, reconstructing the original digital input stream.
According to one implementation of the invention, multiple clock signals may be transmitted along with the original digital data input stream. There is a corresponding number of clock signals and buffers (or buffer regions); moreover, each clock signal has a data rate that is equal to the data rate of the original digital data input stream divided by the number of clock signals.
Each clock signal includes a respective plurality of clocking events, occurring at the specified data rate. The clocking events of the clock signals occur in rotation, one after another in a continuous order. The clocking events of each clock signal identify a different substream of data, interleaved with substreams identified by the other clock signals. The substream of data identified by each clock signal is stored in a separate buffer or buffer region. The data assembler coordinates outputing of the various buffers' substreams, and proper assembling of the substreams to reconstruct the original digital input stream.
Accordingly, in one embodiment, the invention may be implemented to provide a method to transmit and/or receive a digital data input stream. In another embodiment, the invention may be implemented to provide an apparatus such as a transmitter, receiver, or communications exchange subsystem. In still another embodiment, the invention may be implemented to provide a programmed product comprising signal-bearing media tangibly embodying a program of machine-readable instructions executable by a digital data processing apparatus to perform a method for transmitting and/or receiving a digital data input stream.
The invention affords its users with a number of distinct advantages. Chiefly, the invention enables communications subcomponents to exchange digital data without the difficulties that can accompany high speed clock signals. Briefly, this is achieved by using multiple, interleaved clock signals, each having a frequency less than the frequency of the data, to coordinate transmission and receipt of the data. The invention also provides a number of other advantages and benefits, which should be apparent from the following description of the invention.
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Garcia Enrique
Lucas Gregg Steven
Yanes Juan Antonio
Chin Stephen
Dan Hubert & Assoc.
Ghayour Mohammad
International Business Machines - Corporation
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