High speed digital computer data transfer system having reduced

Details High speed digital computer data transfer system having reduced High speed digital computer data transfer system having reduced

1989-08-25

1991-07-09

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307452, 307481, 323315, H03K 19017, H03K 19092, H03K 19096, G11C 1549

Patent

active

050308572

ABSTRACT:
In a high speed digital computer data transfer system, data bus voltage swings between logic high and logic low levels are reduced by defining minimum and maximum bus voltages which lie between said logic levels, thus lowering bus transition and hence data transfer times. The output voltages are converted to the proper logic levels with the aid of a differential (sense) amplifier. The preferred embodiment is implemented using complementary metal-oxide-semiconductor (CMOS) technology.

REFERENCES:
patent: 4488066 (1984-12-01), Shoji
patent: 4498021 (1985-02-01), Uya
patent: 4572972 (1986-02-01), Shoji
patent: 4598216 (1986-07-01), Lauffer et al.
patent: 4670666 (1987-06-01), Yoshida
patent: 4761567 (1988-08-01), Walters, Jr. et al.
patent: 4763023 (1988-08-01), Spence
patent: 4918329 (1990-04-01), Milby et al.

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