High speed digital clock synchronizer

Details High speed digital clock synchronizer High speed digital clock synchronizer

1990-12-28

1993-03-23

Kuntz, Curtis

Pulse or digital communications

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Direct sequence

375120, 328 2, H03D 324

Patent

active

051970864

ABSTRACT:
A synchronization system for locking a data input signal to a local clock uses the data input signal to provide the timing for capturing phase waveforms generated by a delay element string and a local oscillator. A transition detector generates bit patterns which correspond to a captured phase waveform which is in synch with the data input signal. The bit pattern of the captured in synch waveform is stored in a storage device under control of window detection and control logic also timed by the data input signal. The control logic stores a new bit pattern of a new phase waveform when the window detection logic determines that the new bit pattern is outside a 2-bit window and then selects the new phase waveform correponding to the new bit pattern for clocking the data input signal if the new bit pattern hasn't changed after N consecutive cycles of the data input signal.

REFERENCES:
patent: 4677648 (1987-06-01), Zurflush
patent: 4841551 (1989-06-01), Avaneas
patent: 4852124 (1989-07-01), Raucci
patent: 4972444 (1990-12-01), Melrose et al.
patent: 5022056 (1991-06-01), Henderson et al.

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