Coded data generation or conversion – Analog to or from digital conversion – Nonlinear
Reexamination Certificate
1999-05-28
2001-02-20
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Nonlinear
C341S123000
Reexamination Certificate
active
06191716
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to improvements in systems, methods, and circuits for increasing throughput rate and operational speed of a signal processor, and more particularly, to improvements in systems, methods, and circuits to perform the processing necessary to determine “band zero” of a digital signal while separated from the high-speed path in which other parts of the signal are being processed.
2. Relevant Background
In the construction of mass data storage devices, or the like, in particular in the construction of the data channel used in digital magnetic recording systems, or the like, there has been significant recent interest in Partial Response Maximum-Likelihood (PRML) signaling techniques. The most common PRML systems are PR
4
ML (a partial response class
4
) and EPR
4
ML (extended partial response class
4
). Maximum-likelihood detectors, which use a Viterbi algorithm, are generally used in these partial response channels.
The various partial response techniques are generally referred to by the particular partial response target that it uses. For example, a PR
4
partial response target is (1−D)* (1+D), and an EPR
4
partial response target is (1−D)*(1+D)
2
, where D is a delay operator equal to e
j&ohgr;t
, where &ohgr; is frequency, and t is delay time. Recently an EEPR
4
(or E
2
PR
4
) response level has been introduced in which the EEPR
4
partial response target is (1−D)*(1+D)
3
.
In general, the various partial response techniques that are employed use different sampling times at which the signal that is derived from the disk drive transducer are sampled and measured. A PR
4
Partial Response System typically results in data that is contained in three separate bands, often referred to as band
1
, band
0
, and band −
1
. An EPR
4
technique results in sampling bands commonly referred to as band
2
, band
1
, band
0
, band −
1
, band −
2
. The data within the bands is not contained on a single time band value, but instead, have a distribution about the centerline of the band.
In the past, processing the data to separate it into its respective bands required considerable data processing with serial comparisons. Thus, calculation of band data is usually a data processing bottleneck since the subsequent steps rely on it and cannot be performed until the band has been calculated. Therefore, with increased emphasis on high-speed data acquisition and processing, this band determination processing is being regarded as one of the processes that slows the overall processing time for the data.
In general, a “digital signal” is a signal that conveys a discrete number of values at discrete times. This is in contrast an “analog signal,” i.e., a signal that conveys an infinite number of values on a time continuum. A signal having a digital form may be generated from an analog signal through sampling and quantizing the analog signal. Sampling an analog signal refers to “chopping” the signal into discrete time periods and capturing an amplitude value from the signal in selected ones of those periods. The captured value becomes the value of the digital signal during that sample period. Such a captured value is referred to as a sample.
Quantizing refers to approximating a sample with a value that may be represented on a like digital signal. For example, a sample may lie between two values characterized upon the digital signal. The value nearest (in absolute value) to the sample may be used to represent the sample. Alternatively, the sample may be represented by the lower of the two values between which the sample lies. After quantization, a sample from an analog signal may be conveyed as a digital signal. This is the resultant signal soon which the digital circuit may operate.
A digital signal processor (DSP) transforms an input digital signal to an output digital signal. For the digital filter, the transformation involves filtering out undesired portions of the received digital signal. An original analog signal may be represented as a sum of a plurality of sinusoids. Each sinusoid oscillates at a particular and unique frequency. Filtering is used to remove certain frequencies from an input signal while leaving other frequencies intact.
Programs executing on digital circuits often do so in “real-time.” Real-time programs can be regarded as programs that must execute within a certain time interval. Regardless of whether a program executes in a large period of time or a small period of time, the result of executing the program is the same. However, if real-time programs attempt to execute in an amount of time longer than the required time interval, then they no longer will compute the desired result.
Programs executing on a digital circuit are real-time programs, since the instructions manipulate a sample of a digital signal during the interval preceding the receipt of the next sample. If the program cannot complete manipulating a sample before the next sample is provided, then the program will eventually begin to “lose” samples. A lost sample does not get processed; therefore, the output signal of the digital circuit will no longer contain all of the information from the input signal provided to the digital circuit. This potential for losing samples is reduced by a preferred embodiment of the present invention, while maintaining a required throughput rate.
A digital circuit may be programmed to modify signals. The number of instructions required to do this is relatively fixed. The digital circuit must be capable of executing this relatively fixed number of instructions on any given sample before the next sample of the series is provided.
Besides considering the throughput of a digital circuit, most all of the design parameters have associated cost factors that should be considered. One important cost factor is the silicon area needed to “house” the digital circuit. Those circuits that are manufactured on a relatively small silicon chip are less expensive than those requiring a large chip. Therefore, an easily manufacturable, small (low cost) digital circuit is desirable.
A “pipelining” method may be used to achieve better filter performance at high input data rates. One cost of using this method, however, is increased latency. At very high speeds, such as are being seen with newer systems, conventional pipelining falls subject to the law of diminishing returns. The pipelining “overhead” now consumes a larger percentage of the benefits gained from higher clock speeds. The overhead consists of a required latching or reclocking stage for every pipelining command. Generally, the performance improvement for one level of pipelining is less than two while the “on-chip” cost increase is greater than two. All the while this is occurring at the very high clock rate of the input data. The preferred embodiment of the present invention addresses the clock rate limitation imposed by a high data rate input signal, in particular during feedback control operations.
SUMMARY OF THE INVENTION
A preferred embodiment of the present invention provides a system and method for increasing the speed of operation of a high-speed digital circuit, by providing separate paths for processing parts of the input signal, without appreciably increasing “on-chip” real estate.
Processing parts of a signal in separate paths enables optimization of he high-speed portion of a digital circuit, providing adequate time for processing each sample in the high-speed portion. By having one path operate on a calculation intensive portion of the processing and providing for certain operations to be made common to each path, required on-chip area is also reduced compared to conventional digital circuits of comparable performance.
A preferred embodiment of the present invention Is implemented for use by a timing recovery circuit. In a preferred embodiment of the present invention, the signal that is being processed within a timing recovery loop has been previously encoded in a partial response (PR) architecture for further
Brady III Wade James
Le Don Phu
Swayze, Jr. W. Daniel
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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