High-speed digital bus-organized multiplier/divider system

Details High-speed digital bus-organized multiplier/divider system High-speed digital bus-organized multiplier/divider system

1979-03-28

1980-12-09

Malzahn, David H.

Boots, shoes, and leggings

364766, G06F 752

Patent

active

042388333

ABSTRACT:
A bus organized 16.times.16 (or 8.times.8) high-speed digital bus-organized multiplier/divider for high-speed, low-power operation is implemented on a single semiconductor chip. Four working registers each of 16 (or 8) bits are used in the system. These registers are a multiplier register, a multiplicand and divisor register, a first accumulator register for storing the least significant half of a double length product after a multiplication of the remainder after a division operation, and a second accumulator register which stores the most significant half of the product after a multiplication or the quotient after a division operation. A decoder is connected to the multiplicand and multiplier registers to implement the Modified Booth Algorithm and to encode the 16 (or 8) multiplier digits. The system operates to shift the multiplier number through the multiplier register to a position where the Modified Booth Algorithm encoding takes place. The Modified Booth encoder then controls the operation of multiplexer circuits to which the outputs of the multiplicand register are applied to produce successive partial products. A carry/save arithmetic logic unit operates in conjunction with the registers to cause accumulation and storage of multiplication products and division quotient/remainders in the double length accumulator registers which provide a 32 bit output number. BACKGROUND OF THE INVENTION

REFERENCES:
patent: 3730425 (1973-05-01), Kindell et al.
patent: 4065666 (1977-12-01), Wu
patent: 4122527 (1978-10-01), Swiatowiec
patent: 4153938 (1979-05-01), Ghest et al.
patent: 4168530 (1979-09-01), Gajski et al.

Affiliated with

Also associated with

Rating

High-speed digital bus-organized multiplier/divider system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High-speed digital bus-organized multiplier/divider system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High-speed digital bus-organized multiplier/divider system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2284118