High speed differential pre-driver using common mode pre-charge

Details High speed differential pre-driver using common mode pre-charge High speed differential pre-driver using common mode pre-charge

2002-06-28

2004-11-16

Tran, Minh-Loan (Department: 2826)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S079000, C327S331000, C327S333000

Reexamination Certificate

active

06819145

ABSTRACT:

FIELD OF THE INVENTION
The present invention pertains to the field of semiconductor devices. More particularly, this invention pertains to the field of high speed differential drivers and pre-drivers.
BACKGROUND OF THE INVENTION
In an effort to reduce costs and improve performance in today's computer systems, high speed serial differential interfaces are gradually replacing high pin count parallel interfaces to provide communication between computer system components. Bit rates on these interfaces are increasing, and as the bit rates increase, jitter margins decrease accordingly.
High-speed differential transmitters can improve transmitted signal quality by maintaining a consistent crossover point in the bit stream including the first bit and the last bit. The transmitter's jitter can be reduced if the placement of the crossover point is consistent. Typically, the first bit is driven from the ground state while subsequent bits cross over at the common mode voltage. This increases the width of the first bit because of the different crossover point. The width of the last bit is also increased because only one of the differential signals is driven to the ground state. Jitter margin is further decreased with the presence of process skew variations and variations in operating voltages and temperature.
Prior techniques for improving the quality of the first and last bits involve the use of pre-emphasis and selectively boosting the edge rate of the first and/or last bit in order to shorten the rise time. However, with these techniques, the signals are still driven from the ground state, which inherently gives the first and last bits an asymmetry that is not present on the other bits.


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