High-speed, differential pair input buffer

Details High-speed, differential pair input buffer High-speed, differential pair input buffer

1997-11-25

1999-12-07

Wells, Kenneth B.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

327 87, 327 89, H03K 522

Patent

active

059990201

ABSTRACT:
A high-speed, differential pair input buffer is constructed from a conventional differential pair having a data input terminal, a reference voltage input terminal, and an output terminal. A voltage source Vsupply and its ground connection are coupled to the differential pair through a first pair of transistors. The first pair of transistors have their enable inputs coupled to the data input terminal so that they are both biased "on" during a transition in a logic signal delivered to the data input terminal. The output terminal of the differential pair is connected through a delay circuit to the enable input terminals of a second pair of transistors, which also interconnect the differential pair to the voltage source V.sub.supply and system ground. Thus, the second pair of transistors provide a feedback path to enable the differential pair to conduct current longer if a load connected to the output of the differential pair slows the transition of the output of the differential pair.

REFERENCES:
patent: 3991380 (1976-11-01), Pryor
patent: 4769564 (1988-09-01), Garde
patent: 5278467 (1994-01-01), Nedwek
patent: 5596291 (1997-01-01), Runas
patent: 5847581 (1998-12-01), Allen
U.S. Patent Application Serial No. 08/775,785, filed Dec. 31, 1996, entitled "Low Power CMOS Precision Input Receiver with Integrated Reference," by Michael J. Allen (invention disclosure dated Feb. 8, 1996).

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