High speed differential mode voltage controlled ring oscillator

Oscillators – Ring oscillators

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331 34, 331108A, 331176, 331177R, H03B 502, H03K 3354

Patent

active

054263980

ABSTRACT:
A differential mode voltage controlled oscillator (VCO) includes an odd number of delay cells. Each delay cell has a pair of input terminals and a pair of output terminals with the input terminals of each delay cell being connected to the output terminals of a preceding delay cell in a ring. Each delay cell has a delay time for inverting a complementary pair of signals from which a clock signal is derived. A positive temperature coefficient voltage-to-current converter receives the control voltage of the VCO and controls the maximum currents (and therefore the delays) of the delay cells. A pair of cross-coupling transistors in each delay cell keeps the signals on the output terminals out of phase (complementary). The cross-coupling transistors have sizes which maximize gain of the delay cells at the threshold voltages of the cross-couple transistor and thereby increase output voltage swing at high frequencies. The voltage at the output terminals is clamped by transistors having gates coupled to a reference cell. Gate voltage from the reference cell are supplied through a noise reduction filter which reduces jitter in the clock signal by reducing the effect of fluctuations in the supply voltage.

REFERENCES:
patent: 5061907 (1991-10-01), Rasmussen
patent: 5239274 (1993-08-01), Chi
patent: 5300898 (1994-04-01), Chen et al.
Kim et al., "A 30-MHz Hybrid Analog/Digital Clock Recovery Circuit in 2-.beta.m CMOS," IEEE Journal of Solid-State Circuits, vol. 25, No. 6, Dec., 1990, pp. 1385-1394.
Young et al., "WP3.3: A PLL Clock Generator With 5 to 110 MHz Lock Range for Microprocessors," ISSCC 92/ Session 3/High-Performance Circuits/Paper WP 3.3, IEEE Int'l Solid State Circuits Conference, pp. 50-51, Feb. 19, 1992.

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