High-speed differential flip-flop

Details High-speed differential flip-flop High-speed differential flip-flop

2001-11-26

2004-11-16

Nguyen, Long (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S208000, C327S211000, C327S218000

Reexamination Certificate

active

06819156

ABSTRACT:

BACKGROUND
Logic circuits can be classified into two broad categories, combinational logic circuits and sequential logic circuits. The basic building block of sequential logic circuits is the flip-flop, also called a bi-stable multi-vibrator or latch. In most cases, logic circuits employ both sequential and combinational logic.
FIG. 1
(prior art) depicts an exemplary logic circuit
100
that includes both combinational and sequential logic elements. Logic circuit
100
is a divide-by-five counter
100
with a pair of NOR gates
105
in a feedback path of a series of differential-input flip-flops
110
. Circuit
100
receives a pair of complementary clock signals C and Cb, which extend to clock input terminals of each of the flip-flops
110
. Circuit
100
produces a pair of complementary clock signals C/
5
and Cb/
5
with a frequency one fifth that of the input clock signals. The differential nature of circuit
100
allows for higher clock frequencies than would a similar divide-by-five circuit using single-ended sequential logic elements.
FIG. 2
(prior art) depicts an embodiment of a differential-input flip-flop
110
for use in circuit
100
of FIG.
1
. The operation of flip-flop
110
is commonly understood by those of skill in the art, so a detailed description of flip-flop
110
is omitted here for brevity.
If manufactured using commonly available CMOS processes, flip-flop
110
can perform with clock frequencies as high as about 2 GHz. Unfortunately, modern high-speed digital communication systems employ clock and data recovery circuits operating in the 10 Gb/s range. The frequency response of flip-flop
110
is therefore insufficient to meet the needs of some modern systems.
SUMMARY
The present invention is directed to high-speed flip-flops. A flip-flop in accordance with one embodiment of the invention has a differential input stage that incorporates some combinational logic. This embodiment improves speed performance by reducing or eliminating the need for separate combinational logic circuits when the flip-flop is employed in certain circuit configurations. In one example, a flip-flop incorporating combinational logic is used in conjunction with other flip-flops to create a counter circuit that would otherwise require separate combinational logic.
A flip-flop in accordance with another embodiment of the invention includes differential input and output stages, each of which includes a transistor connected across its differential output terminals. The transistors are clocked to short the differential output terminals between expressions of logic levels, thereby limiting the maximum amount of voltage swing required to express subsequent logic levels.
This summary does not define the scope of the invention, which is instead defined by the appended claims.


REFERENCES:
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patent: 5384493 (1995-01-01), Furuki
patent: 5777491 (1998-07-01), Hwang et al.
patent: 6002270 (1999-12-01), Timoc
patent: 6337583 (2002-01-01), Ooishi et al.
patent: 6373292 (2002-04-01), Choe
patent: 6433586 (2002-08-01), Ooishi
patent: 2003/0052720 (2003-03-01), Tung et al.
patent: 2000244287 (2000-09-01), None

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