High-speed differential decoder with reduced area consumption

Details High-speed differential decoder with reduced area consumption High-speed differential decoder with reduced area consumption

1999-04-22

2001-04-10

Williams, Howard L. (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S144000, C341S155000

Reexamination Certificate

active

06215436

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a high-speed differential decoder with reduced area consumption. More particularly, the present invention relates to a differential decoder used, for example, in a high-speed flash analog/digital converter.
BACKGROUND OF THE INVENTION
A known converter, for example a flash converter such as the one shown in
FIG. 3
, includes a plurality of comparators
1
, which receive an input signal Vin in addition to a reference signal generated by a string of resistors
2
. Depending on the value of the input signal Vin, the comparators can have an output signal which is higher than the input signal, for example, a logic value of 1, or the comparator can have an output signal which is lower than the input signal, a logic value of 0. Therefore, at the output of the comparators, a plurality of bits are obtained in which some have the logic value 1 and others have the logic value 0. Accordingly, the output is a thermometer code, which must be converted into a more suitable code, for example, a Gray code.
The logic circuit
3
shown in
FIG. 3
is designed to convert the thermometer code output from the comparators
1
into a code in which, for example, all the bits have the value 0 except for the single bit that indicates the value of the input signal Vin. The logic value 1 output from the logic circuits
3
indicates the transition point, i.e. the point at which the output signal of the comparator changes from the value 1 to the value 0 or vice versa. The object is to output a numeric code which is the equivalent of the input signal Vin. Therefore, the logic circuits
3
, which are usually gates of the NOR or NAND type, output a plurality of bits, only one of which is different from all the others.
A PLA type decoder
4
is cascade-connected to the logic circuits
3
. It appropriately decodes the signal received from the logic circuits
3
in order to output a signal which indicates the value of the input signal Vin.
FIG. 2
illustrates an example of a known type of PLA which shows, by way of example, only three inputs IN
0
, IN
1
, IN
2
and three outputs OUT
0
, OUT
1
, OUT
2
. In
FIG. 2
, the output lines designated by OUT
0
-OUT
2
are connected to the inputs IN
0
-IN
1
through a plurality of transistors of the NPN type. In particular, the transistors
10
and
11
are connected to the input IN
2
and their base and collector terminals are common-connected and connected to the output lines OUT
2
and OUT
1
respectively. The transistors
12
and
13
are instead connected to the input IN
1
and their base and collector terminals are common-connected and connected to the output lines OUT
2
and OUT
0
respectively. Finally, the transistor
14
is connected to the input IN
0
and to the output line OUT
1
.
All the NPN bipolar transistors
10
-
14
are connected to the supply voltage by their respective collector terminals. Current sources
15
,
16
and
17
are provided for the output lines.
The above-proposed structure, shown in
FIG. 2
, suffers the drawback caused by the output dynamic range of the signal being limited by the need to have high speed logic circuits
3
(as shown in
FIG. 3
) upstream of the PLA decoder
4
. Accordingly, the output signal may not be determined with certainty, because the difference in voltage levels between a logic value 1 and a logic value 0 is very small.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a differential decoder with a wide output dynamic range and with reduced area consumption which substantially improves the output dynamic range of the signal, avoiding the possible uncertainties of the prior art. Within the scope of this object, a purpose of the present invention is to provide a differential decoder which increases the dynamic range of the output without introducing complementary devices.
Another object of the present invention is to provide such a differential decoder which achieves signal
oise ratio advantages on the subsequent processing of the output signal. Another object of the present invention is to provide such a differential decoder which allows the use of fully differential ECL (Emitter Coupled Logic or Current Mode Logic) logic circuits. Still another object of the present invention is to provide such a differential decoder which can eliminate the uncertainty of the output signal from the logic circuits upstream of the decoder. Furthermore, another object of the present invention is to provide such a differential decoder which is highly reliable, relatively easy to manufacture and cost competitive.
These objects and others which will become apparent hereinafter are achieved by a differential decoder with a wide output dynamic range and reduced area consumption comprising a plurality of inputs which are correlated to a plurality of output lines. The output lines are driven by respective NPN type bipolar transistors which are connected to the output lines by their emitter terminals. The input signals are fed to their base terminals. The decoder further comprises a plurality of additional output lines which are complementary to the output lines and another plurality of NPN type bipolar transistors which are suitable to drive the additional output lines. The additional bipolar transistors are connected to the additional output lines by their emitter terminals and connected to the base and collector terminals, of the bipolar transistors that drive the output lines, by their base and collector terminals.


REFERENCES:
patent: 4292625 (1981-09-01), Schoeff
patent: 4568910 (1986-02-01), Sekino et al.
patent: 5315301 (1994-05-01), Hosotani et al.
patent: 5644312 (1997-07-01), Deevy et al.
patent: 5886653 (1999-03-01), Ishigami

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