High speed differential data latch

Details High speed differential data latch High speed differential data latch

1996-03-07

1998-09-01

Wambach, Margaret Rose

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327 52, 327 57, 327203, H03K 3289

Patent

active

058015655

ABSTRACT:
A high speed differential data latch includes identical master and slave flip-flops. The master flip-flop is driven by a differential input data signal while both flip-flops are driven by a shared differential clock signal. Each flip-flop includes: one differential amplifier for sequentially latching the differential input data signal to provide a differential output data signal; a second differential amplifier for generating two switched supply currents from the clock signal for powering the differential data amplifier; and a third differential amplifier cross-coupled to the differential data amplifier for providing positive feedback thereto for enhancing the latching speed. The differential output data signal follows the differential input data signal during one of the differential clock states and remains latched during the other differential clock state.

REFERENCES:
William R. Blood, Jr., "MECL System Design Handbook", Fourth Edition, 1988, pp. 12-14.

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