High speed differential comparator

Electrical transmission or interconnection systems – Personnel safety or limit control features – Interlock

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307291, 307530, H03K 524

Patent

active

053329317

ABSTRACT:
A differential comparator with inputs switched and capacitively coupled to inverters which have capacitive cross-coupling feedback for a latching operation. The inverters also have direct switched feedback for autozeroing. The inputs further have a shorting switch between the input switches and the coupling capacitors for offset compensation. Complementary operation of the switches provides precharge and evaluation phases of operation. During precharge the inputs are applied to the input coupling capacitors and the inverters are autozeroed; during evaluation the inputs are transferred to the inverters through the coupling capacitors and the outputs feedback positively through the cross-coupling capacitors to latch the pair of inverters.

REFERENCES:
patent: 4374334 (1983-02-01), Eageler
patent: 4547683 (1985-10-01), Bingham
patent: 4802130 (1989-01-01), Soneda
patent: 4803382 (1989-02-01), Tanimoto et al.
patent: 4883897 (1989-11-01), Fattaruso
patent: 4899068 (1990-02-01), Klose et al.
patent: 5032744 (1991-07-01), Liu
Electronic Circuit Design Handbook, 4th Edition Revised, pp. 131 and 134-140 (1971).
"Monolithic Expandable 6 Bit 20 MHz CMOS/SOS A/D Converter" Dingwall, IEEE Journal Of Solid-State Circuits vol. SC-14 #6 Dec. 1979, pp. 926-932.
Modern Electronic Circuits Reference Manual, Markus, pp. 161-169 (1980).

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