High-speed demultiplexer circuit

Details High-speed demultiplexer circuit High-speed demultiplexer circuit

1987-10-16

1988-12-13

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

328105, H04J 302

Patent

active

047916281

ABSTRACT:
A demultiplexer for demultiplexing a multiplexed input data signal into M output channels using M sequencer means clocked from an overlapping M phase system clock. The system clock operates at a frequency equal to the input data signal rate divided by M. Each sequencer means is clocked by a unique combination of the M phase system clock signals to select one data channel from the multiplexed input data signal. Since all sequencer means circuits are synchronized to the system clock, no variable delay lines are needed to align the timing between the circuit stages. A time delay latch is provided where needed in each sequencer means to enable all channels to output data concurrently. The demultiplexer includes a real-time data-framing capability to assure that the input data is correctly mapped to the proper output channels.

REFERENCES:
patent: 3921079 (1975-11-01), Heffner et al.
patent: 4317198 (1982-02-01), Johnson
H. M. Rein and R. Reimann, "6Gbit/s Multiplexer and Regenerating Demultiplexer ICs for Optical Transmission Systems Based on a Standard Bipolar Technology", Electronics Letters, vol. 22, No. 19, Sep. 11, 1986, pp. 988-990.

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