High speed delta-sigma A/D converter using a quantized USM...

Details High speed delta-sigma A/D converter using a quantized USM... High speed delta-sigma A/D converter using a quantized USM...

1998-03-30

2001-02-13

Wamsley, Patrick (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Differential encoder and/or decoder

C341S155000

Reexamination Certificate

active

06188345

ABSTRACT:

FIELD OF INVENTION
Our invention relates to A/D converters and more particularly to high speed delta-sigma A/D converters.
BACKGROUND
FIG. 1
shows a conventional first-order “1-bit” delta-sigma modulator (DSM) for analog-to-digital (A/D) converting a series of sample inputs X
i
into a 1-bit quantized signal y
i
. It consists of an integrator
10
followed by a two-level (1-bit) comparator
12
with a negative feedback loop back to the input. The comparator
12
is clocked at some rate f
s
and generates a stream of decisions y
i
at the integrator output. The stream of decisions y
i
is fed back to the input to be subtracted from the stream of input samples x
i
. Typically f
s
is several times higher than the Nyquist rate so that the 1-bit digital output y
i
is oversampled. The oversampled digital output can then be passed to a decimation filter (not shown) which averages the values to produce an n-bit result at a lower frequency.
The standard analysis of the operation of a DSM A/D converter uses a linear system approximation. The quantization error is assumed to be additive white gaussian noise, and it can be shown that this noise is shaped by a high-pass characteristic. This approximate explanation avoids the difficulties involved in a non-linear analysis, but it is limited in practice. It fails to predict important phenomena and suggests some erroneous behavior, mostly because the quantization error is actually deterministic and strongly correlated with respect to the input.
One can think of the integrator output as consisting of two sums: the sum of the input samples x
i
, and the negative of the sum of the comparator decisions y
i
(either V
r
or−V
r
). The negative feedback loop operates to keep the integrator output bounded, in which case
∑
i
N
⁢
&LeftBracketingBar;
x
i
-
y
i
&RightBracketingBar;
<
∼
V
r
(
Eq
.
 
⁢
1
)
where y
i
&egr;{V
r
,-V
r
} and N is a certain number of decisions.
This implies that
{overscore (x)}={overscore (y)}+V
r
/N  (Eq. 2)
where {overscore (x)} is an average over N values of x
i
. Thus the modulator seeks to make the average of the output decision stream equal to the average of the sequence of input values.
FIG. 2
illustrates this behavior. It shows a highly oversampled input sinusoid together with the corresponding DSM output values from both first and second order structures. (The output levels are arbitrary.) Observe that in the vicinity of the positive input peak, the first-order system output values assume a limit cycle of frequency f
s
/4. In general, there is a limit cycle corresponding to each DC input level, and some of these limit cycle frequencies fall in the signal baseband.
Higher order DSM architectures use more integrators to effectively break up lower frequency limit cycles into higher frequencies, as illustrated by the second order outputs in FIG.
3
. Higher order architectures generate the same decision rate with similar properties with respect to the signal, but with limit cycles shifted to higher frequencies. This is a more general fact describing the non-linear behavior of DSM than the usual noise-shaping argument from the linear approximation to DSM.
Note that a simple average over N output decisions can give a resolution only to 2V
r
/N, so even with N=256, only 7-bit resolution would be achieved. Thus, the filter coefficients must be weighted.
Another typical way of looking at the operation of a DSM is to write the difference equations describing the discrete-time system shown in FIG.
3
.
It can be shown [1] that the system of
FIG. 3
satisfies the equation
y
i
=x
i−1
+(e
i
−e
i−1
)  (Eq. 3)
where e
i
is defined to be the quantization error e
i
≡y
i
−w
i
and y
i
∈{V
r
,−V
r
}. Note that for simplicity in
FIG. 3
we have not explicitly shown a digital-to-analog (D/A) converter in the feedback path. It should be understood that the digital output can be any arbitrary pair of binary symbols, and that the feedback must be some appropriate pair of reference analog circuit reference quantities, here denoted {V
r
,−V
r
}.
According to equation 3, the term added to each input sample is the first difference of the quantization error, which suppresses the low-frequency components of the error. This effect is the familiar noise-shaping property of the DSM.
A frequency-response picture of the operation of first and second-order DSMs is shown in FIG.
4
. The frequency response of a typical “sinc
3
” filter is superimposed over the Discrete Fourier Transforms (DFT) of the 1-bit output streams of the modulators. The abscissa of the plot is linear normalized digital frequency where unity corresponds to the sample frequency. Note that this particular plot only covers the frequency interval [0, 0.03]. The sinc filter has zeros at multiples of {fraction (1/64)}. The simulation input was a sinusoidal tone at a normalized frequency of 67/16384.
The DFTs in
FIG. 4
clearly show the noise-shaping behavior of the modulators, i.e. the noise floor dramatically rolls off as the frequency approaches DC. This plot graphically illustrates how high signal to noise ratio (SNR) can be obtained from DSM by high oversampling and filtering with a lowpass filter. Of course, the drawback to high oversampling is that the allowable signal bandwidth is reduced, relative to the sampling frequency, by the oversampling ratio (OSR).
In summary, the standard delta-sigma data conversion technique achieves high resolution with very simple analog circuitry which can be made very robust with respect to component variation.
It is very desirable to explore methods of using the delta-sigma algorithm in data conversion architectures that trade increased circuit complexity for reduced oversampling ratio. In particular, the hardware requirements of flash converters grow faster than exponentially because the number of comparators grows exponentially with bits of resolution, and for improved matching the size of the comparator input devices tends to grow as the square root, with increasing resolution. Therefore, there is a need for fast data conversion architectures that grow less rapidly and possess more robust properties with respect to component variation.
The standard DSM technique uses temporal oversampling, where the oversampling factor is obtained by sequentially obtaining input samples with a single sampling block. As an alternative, it is possible to achieve oversampling spatially by using parallel sampling blocks. As previously mentioned, there is strong motivation to trade off temporal oversampling for spatial oversampling.
There are several existing approaches to parallelism with delta-sigma modulation data conversion. One approach is to use time-interleaved standard DSMs [2]. The signal is sampled by N identical parallel DSMs which are clocked at the same frequency but on distinct phases of an N-phase clock.
Another approach, shown in
FIG. 5
, uses Hadamard modulation to separate the input into N parallel, orthogonal data streams, which are then fed to N parallel DSM units
20
1
,
20
2
,
20
3
, . . . ,
20
N
[3]. The outputs are demodulated and filtered.
But these prior art architectures have inherent design limitations that our invention improves upon.
SUMMARY OF THE INVENTION
Rather than using parallel standard modulators, our approach seeks to create fast DSM architectures by “unraveling” the standard delta-sigma decision algorithm into a spatial structure, much as a “pipelined” A/D converter is obtained by unraveling a successive-approximation loop.
More particularly, our high speed sigma-delta A/D converter for a sequence of analog samples x
n
(n=0, 1, 2, . . . N−1) has an input, a plurality N−1 of phase clocks CLK
n
, a plurality of sample-hold circuits, a plurality N−1 of circuit stages, and a D/A converter. The input receives the analog samples x
n
. The sample-hold circuits SH
n
are coupled to the input and each r

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