High speed decoder for flash memory

Details High speed decoder for flash memory High speed decoder for flash memory

2001-04-30

2003-11-11

Nguyen, Van Thu (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S189090, C365S226000, C365S233500, C365S241000, C365S185130

Reexamination Certificate

active

06646950

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to decoders for flash memories, and more particularly to a fast xdecoder using NMOS driver circuitry in combination with a time delay scheme to insure efficient boost operation.
BACKGROUND OF THE INVENTION
Flash memories conventionally consist of an array of floating gate transistors or core cells that are arranged in blocks and are individually addressable by energizing a specific word line and a specific bit line of the array. A “0” on a core cell corresponds to a high turn-on threshold voltage on the order of 4V for the cell, while a “1” corresponds to a low turn-on threshold voltage on the order of 2V. The word line for each cell is connected to its transistor's control gate, and the bit line for its address powers its source-drain circuit. A cell is read by driving its word line to a voltage between the above-mentioned threshold voltages while its source-drain circuit is energized. If current flows, the cell contains a “1”; if not, it contains a “0.”
Traditionally, word line driver circuits for flash memories have been executed in CMOS topologies. These topologies have worked well with conventional robust V
CC
sources of 5V or more, where parasitic cell capacitances were not a significant consideration. In recent times, however, increasing miniaturization of electronics in general, and flash memories in particular, have led to smaller V
CC
supplies, on the order of 3V.
Because of this lower V
CC
, it is necessary to use a voltage boosting circuit to provide a boost voltage V
BST
to the control gate. Such a circuit is quite sensitive to parasitic capacitance loading. It is in the nature of a CMOS driver for an xdecoder that its global word line must be low in order for the cell to be selected. Consequently, the word lines of all unselected cells must be high, a condition which loads the boost circuit and slows it down. Thus, for fast operation, it is desirable to provide a way of increasing boosting without loading the boost circuit.
SUMMARY OF THE INVENTION
The present invention solves the above-described problems by providing word line drivers using NMOS transistors, in combination with a time-delay addressing scheme that uses the driver transistors' gate capacitance to provide an extra boost.


REFERENCES:
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patent: 6026047 (2000-02-01), Ryu et al.
patent: 6198685 (2001-03-01), Sudo et al.
patent: 6229755 (2001-05-01), Oh
patent: 6255900 (2001-07-01), Chang et al.
patent: 6347052 (2002-02-01), Akaogi et al.
patent: 05-120881 (1993-05-01), None
patent: 07-045074 (1995-02-01), None

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