High speed decoder

Pulse or digital communications – Receivers – Particular pulse demodulator or detector

Reexamination Certificate

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Details

C714S794000

Reexamination Certificate

active

10322874

ABSTRACT:
A branch metric duplication method substantially reduces interconnection delays. The branch metric duplication method is particularly useful to implement a high speed radix-4 Viterbi decoder targeted for FPGA applications. The decoder includes a plurality of branch metric computation units (BMCUs), at least one add-compare-select unit (ACSU) having a plurality of cells, and a survivor path memory unit (SMU). The plurality of BMCUs, the at least one ACSU, and the SMU are configured to implement the decoder.

REFERENCES:
patent: 5729517 (1998-03-01), Fujiwara et al.
patent: 6373413 (2002-04-01), Yoshinaka
patent: 6674816 (2004-01-01), Shieh
patent: 6732326 (2004-05-01), Choi et al.
patent: 2003/0101403 (2003-05-01), Jeon et al.

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