High speed data transfer system which adjusts data transfer spee

Details High speed data transfer system which adjusts data transfer spee High speed data transfer system which adjusts data transfer spee

1989-01-13

1993-08-17

Lee, Thomas C.

Boots, shoes, and leggings

364271, 3642711, 3642601, 364229, 364DIG1, 395500, G06F 1314

Patent

active

052376761

ABSTRACT:
A computer system bus includes signal lines for controlling a high speed block data transfer mode between a bus master and a bus slave. When both devices support such a transfer, a high speed bus clock separate from the normal bus clock is used to transfer data. Devices not involved in the high speed block transfer see only an extended normal data transfer. The master and slave use bus control signals to determine the speed and data width of the high speed transfer. If the slave is unable to transfer the complete block of data at the high speed clock rate, it can signal the master to repeat the transfer of individual data items as necessary.

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Technical Disclosure Bulletin, Apr. 1986, vol. 28, No. 11, pp. 4837-4839.

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