High speed data transceiver

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307456, 3072966, 307270, H03K 19692, H03K 301

Patent

active

052668479

ABSTRACT:
The driver stage of a high speed multi-channel data transceiver in accordance with the present invention includes a bias voltage regulator that regulates base drive for each transceiver driver stage to achieve fast and stable propagation delay over varying supply and temperature conditions. An input capacitor connected to the voltage bias input line provides instant base drive to the output driver for fast turn-on without adding DC current. Two pairs of Miller capacitor transistors connected between the transceiver's driver stage data input and the collector of the output driver control driver output slew rate. A discharge capacitive network connected to the base of the output driver provides an instant discharge path when the driver is disabled.
On the receiver side, an ECC-to-TTL converter stage reduces node capacitance and provides fast turn-off. A TTL output buffer that uses the backplane transceiver logic ground as ground consumes zero power when the receiver is in the high impedance state.

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Boris Bertolucci; Fastbus Dual-Port memory and Display Diagnostic Module: IEEE Transaction on Nuclear Science, vol. NS-34, No. 1, Feb. 1987; pp. 253-275.

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