High speed data synchronizer

Pulse or digital communications – Spread spectrum – Direct sequence

Patent

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Details

307523, H04L 708

Patent

active

051329905

ABSTRACT:
A synchronizer which samples and stores the synchronized data with a transparent latch instead of a flip-flop or similar device to avoid the long set-up times required by such devices. The synchronizer compares its input level to its output level. When they are found to be different because of an input data change, the difference is used to gate the system clock, which in turn gates the transparent latch to sample and store the changed input data level as the new data output level. Since the change in the input data gates the system clock which further gates the opening of the latch, the input data is essentially guaranteed to fulfill the latch set up time requirements. For the difficult case when the input data change occurs as the clock is changing states, a Schmitt trigger is inserted ahead of the latch gating input. The Schmitt trigger will either respond and provide a proper pulse width and magnitude to drive the latch without metastability, or it will pass a "runt pulse" and not respond to it. The latch gating input likewise will not respond to the "runt pulse" because of the pulse's insufficient duration or level. Thus, the Schmitt trigger acts as a matched filter to prevent metastability problems from any runt pulses.

REFERENCES:
patent: 4362957 (1982-12-01), Stern
patent: 4422176 (1983-12-01), Summers
patent: 4446389 (1984-05-01), Williams et al.
patent: 4471235 (1984-09-01), Sakhuja et al.
patent: 4527080 (1985-07-01), Zweig
patent: 4529892 (1985-07-01), Reilly et al.
patent: 4549094 (1985-10-01), Floyd
patent: 4965814 (1990-10-01), Yoshida et al.

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