High speed data modification system and method

Coded data generation or conversion – Digital code to digital code converters – Adaptive coding

Reexamination Certificate

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Details

C370S389000

Reexamination Certificate

active

06268808

ABSTRACT:

The present invention relates generally to high speed data communications, and particularly to a method and system for altering high speed fibre channel data in a user specified manner.
BACKGROUND OF THE INVENTION
FIG. 1
illustrates, in block diagram form, High Speed Data Channel System
30
. High Speed Data Channel System
30
includes two Devices
32
and
34
that communicate via duplex High Speed Data Channel Path
36
. High Speed Data Channel Path
36
consists of Data Path A
38
and Data Path B
40
. Data Path A carries a digital traffic stream from Device
32
to Device
34
, while Data Path B carries a digital traffic stream from Device
34
to Device
32
.
Each traffic stream carries at least two types of digital data, each having its own format. (The term “datum” is used herein to refer to a single item of data, regardless of its type or format.) One data type is the link delimiter. A link delimiter is a set of bits, normally ranging from 8 to 32 bits, in multiples of 8, that are used for various synchronization purposes. Within the fibre channel protocol link delimiters are called ordered sets, of which there are several types, including, for example, OPN, CLS, RRDY and IDLE. Another data type is the frame. According to the frame format, a frame begins with a Start of Frame delimiter (SOF), followed by a header, payload, and Cyclical Redundancy Check (CRC), and ending with an End of Frame delimiter (EOF). There are several types of SOFs and EOFs, any one of which may be included in a frame. A frame header is a combination of a channel header, followed by other optional high level headers, and other, optional, application specific headers. Both the frame header and payload include a multiplicity of words. According to High Speed Data Channel conventions, a word includes 32 bits, which is equivalent to 40 bits of serial data transfer.
As high speed data communications mature, designs increasingly focus on reliability and performance issues. Thus, a need exists for means of altering channel data, including introducing errors into channel data paths, and for monitoring system response to the altered data. As used herein, “system” includes all the hardware and software sub-systems. Such a means of altering data would enable system designers to determine, for example:
1. whether a system responded appropriately to incomplete, misplaced or missing tasks or sequences;
2. how misdirected or confusing frames are treated; and
3. how misplaced ordered sets are treats.
Simulating these types of errors permits realistic modeling of complex link and subsystem errors.
SUMMARY OF THE INVENTION
The Data Modifier of the present invention enables testing of High Speed Channel Systems response to altered data. The Data Modifier modifies channel data in a user specified manner response to a user predefined trigger. Absent trigger detection, the Data Modifier operates in a pass-through mode, outputting unmodified traffic. Briefly described, the Data Modifier of the present invention includes a Trigger Subsystem and a Modification Subsystem. The Trigger Subsystem generates a trigger signal when it detects the presence of a user predefined pattern in a first input datum of an input data stream. The Modification Subsystem responds to the trigger signal by altering user specified portions of the first input datum of the input data stream to create a corresponding output datum having a fixed, real-time delay with respect to the first input datum.


REFERENCES:
patent: 4999837 (1991-03-01), Reynolds et al.
patent: 5001712 (1991-03-01), Splett et al.
patent: 5008885 (1991-04-01), Huang et al.
patent: 5276690 (1994-01-01), Lee et al.
patent: 5983275 (1999-11-01), Ecclesine
patent: 6088354 (2000-07-01), Lenell

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