High speed data interface buffer for digitally controlled electr

Details High speed data interface buffer for digitally controlled electr High speed data interface buffer for digitally controlled electr

1980-12-24

1983-06-07

Krass, Errol A.

Boots, shoes, and leggings

2504922, 364200, H01J 3728

Patent

active

043874339

ABSTRACT:
An electron beam exposure system for forming integrated circuit patterns in which pattern data provided by either a control processor or a mass storage device is transferred through a pattern buffer interface which contains a large buffer memory, the reading and writing of which is automatically controlled by read and write logic contained within the interface. Data is transferred to the interface over busses having a data width less than the data width capable of being stored at an addressable location in the buffer memory. Automatic assembly of larger units of data is controlled by logic within the interface which requires only initialization by the control processor. Automatic address sequencing for subsequent data transfers is carried out under control of self-incrementing storage address registers and self-decrementing word count registers. Transfers of data to the electron beam column, through a pattern generator, is provided in addressable data units, while transfers to the control processor or mass storage device are provided as sub-units of an addressable data unit compatable with their respective buss widths.

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