High speed data bus system

Details High speed data bus system High speed data bus system

1981-10-21

1984-11-06

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 92, 3701101, H04J 312

Patent

active

044816251

ABSTRACT:
In a high speed data bus system, each functional unit has an associated port which operates to accept all related information that makes up a communication, or if this cannot be done, to accept none of the information. More particularly, an information transfer, depending on its nature, may comprise one BIQ or more than one BIQ (a "BIQ" is a bus information quantum which is placed on the bus for one bus cycle). To implement the indivisibility of multiple-BIQ transfers, the control logic for each port includes screening circuitry responsive to the state of the port's input buffers, and further responsive to flags from the functional unit for selectively accepting or rejecting BIQ's, and further includes screening constraint circuitry to ensure that the port accepts all or none of the BIQ's that make up the transfer. Depending on the flag, the rejection may be total, or may apply only to a designated class of transfers (for example, operations).

REFERENCES:
patent: 3787627 (1974-01-01), Abramson et al.
patent: 4236245 (1980-11-01), Freeny et al.
patent: 4354263 (1982-10-01), Bordry et al.

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