High speed data bus structure

Details High speed data bus structure High speed data bus structure

1986-04-10

1988-04-05

Zazworsky, John

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307262, 307254, 307455, 307494, H03K 1921, H03K 19086, H03K 1762

Patent

active

047361247

ABSTRACT:
A very high speed data bus system for communication among the various functional units that may constitute a large computer system. The bus communication medium comprises a number of line pairs on the backplane, and the bus system comprises a bus control unit for arbitrating requests from a plurality of interface units or ports, there being one such port associated with each functional unit. The functional units are densely packed, that is, mounted in immediately adjacent connectors to define a populated section of the backplane in which all connectors have ports coupled thereto, and one or two unpopulated sections of the backplane in which the connectors are empty. In the populated section, the effective characteristic impedance, designated Z.sub.O ', is lower than the effective characteristic impedance, designated Z.sub.O, in the unpopulated region. A populated end of the transmission line is resistively terminated with a resistance corresponding to Z.sub.O ' while the unpopulated end is terminated with a resistance corresponding to Z.sub.O. The border between the populated and unpopulated sections is terminated with a resistance corresponding to 1/(1/Z.sub.O '-1/Z.sub.O), designated Z.sub.O ", thus eliminating signal reflections that could compromise data integrity and degrade system performance.
The two lines that define each differential line pair may be effectively crossed over between successive connectors on the backplane so that an individual line is connected alternately to the positive and negative receiver input terminals at successive ports. Driver gating circuitry responsive to first and second data input signals, an enable signal, and a conditional inversion input signal performs multiple levels of gating with a minimum of propagation delay. The preferred differential receiver amplifies a relatively low level differential input signal and performs an exclusive or function with a conditional inversion signal with a miniumum propagation delay between the signal input and an output line pair.

REFERENCES:
patent: 3432650 (1969-03-01), Thompson
patent: 4256980 (1981-03-01), Asada et al.
patent: 4258274 (1981-03-01), Nagashima et al.
patent: 4308471 (1981-12-01), Misawa
patent: 4435656 (1984-03-01), Tomuro

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