High-speed D flip-flop

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit

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Details

327210, 327211, 327212, H03K 3356

Patent

active

060609273

ABSTRACT:
A high-speed flip-flop is provided that implements a low power consumption and a high-speed response caused by an interior capacitance reduction. A D flip-flop includes a first latch that receives a clock signal and a data signal to produce a first output signal. A second latch receives the first output signal and the clock signal to produce a second output signal. A third latch receives the second output signal and the clock signal to produce a third output signal. An inverter receives the third output signal to produce the data signal on a rising or falling edge of the clock signal. The first and second latches are preferably ratioed latches having series coupled pull-up and pull-down elements. The third latch is preferably a clock operated latch.

REFERENCES:
patent: 4057741 (1977-11-01), Piguet
patent: 5592114 (1997-01-01), Wu et al.
"A True Single Phase Clock Dynamic CMOs Circuit Technique" by Ji-Ren et al., IEEE Journal of Solid State Circuit vol. SC 22. No. 5, Oct., 1987, pp. 899-901.
"A Robust Single Phase Clocking for Low Power, High-Speed VLSI Applications" by Afghahi, IEEE Journal of Solid State Circuit, vol. 31, No. 2, Feb. 1996, pp. 247-253.
"High-Speed CMOS Circuit Technology" IEEE Journal of Solid-State Circuits, vol. 24, No. 1, Feb. 1989, pp. 62-63.

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