Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2002-10-01
2003-04-29
Elms, Richard (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S189011, C365S200000, C365S230030
Reexamination Certificate
active
06556507
ABSTRACT:
BACKGROUND OF THE INVENTION
This application is based on Japanese Patent Application No. 10-124367, filed May 7, 1998, Japanese Patent Application No. 10-203454, filed Jul. 17, 1998, and U.S. patent application Ser. No. 09/305,752, filed May 6, 1999, now U.S. Pat. No. 5,973,991, issued Oct. 26, 1999 the contents of which are incorporated herein by reference.
The present invention relates to a semiconductor memory for configuring an SDRAM (Synchronous DRAM) which needs to operate at a high-speed, and more particularly high-speed cycle clock-synchronous memory and memory system using the same.
SDRAM has banks comprising, for example, a plurality of memory cell arrays (referred to as “cell array” below). A sense amplifier zone in each bank is shared by cell arrays adjacent thereto. Configuration of such a sense amplifier area is allowed to reduce an area occupied by the same. Also, an input/output data line may be shared by each cell array. Data is transferred to a buffer for output data burst via such shared data lines.
When data in an arbitrary cell array is accessed, all of cell arrays in the bank including the accessed cell array are controlled all at once. That is, a word line (WL) in an arbitrary cell array to be accessed is activated to be an active level, and data of each memory cell belonging to this WL is temporally stored by each sense amplifier.
Thereafter, arbitrary data is read out via an input/output data line. Data of each memory cell belonging to the above-mentioned word line WL is restored. After the WL is set at an inactive level, a bit line and the sense amplifier are equalized. Then, an arbitrary cell array in the bank can be subjected to the next activation.
FIG. 14
is a timing chart showing an example of data access design, according to the prior art described above. /RAS (Row Address Strobe) signal (the leading “P, is capped with a horizontal bar in the drawings) makes a word line of a selected cell array active during “L” (low level). As a result, it becomes possible to access data in each memory cell belonging to the selected WL, that is, the page data.
A value of address (Add) at the time when /RAS signal falls to “L” designates a cell array and a word line (WL) to be selected (as denoted by (R)). Thereafter, each time /CAS (Column Address Strobe) signal (the leading “P, is capped with a horizontal bar in the drawings)falls, a page address is determined (as denoted by (C
1
) to (C
4
)). Accordingly, data is output from a sense amplifier in a column corresponding to the page address.
For internal operation, during a period in which /RAS is set at “L”, data in each memory cell belonging to the word line WL in the activated cell array is kept in the state of sense, amplified (stored condition) and restore state (S&R). EQL is an equalizing operation of a bit line and a sense amplifier. EQL functions after /RAS becomes “H” (high level) and the word line WL becomes an inactive level.
Such a data access operation enables high-speed access to data in a memory cell belonging to a selected word line WL. However, such high-speed access as mentioned above cannot be maintained when selection of the WL is frequently changed. This is because access to a column cannot be performed until selection of a new word line becomes possible.
Regarding access to data in cell arrays in the same bank, attention should be paid to a time from completion of selecting one word line WL
1
until it is possible to select another word line WL
2
.
Selection of the word line WL
2
is prohibited until EQL of the internal operation in
FIG. 14
is terminated, regardless of the memory cell that the WL
2
belongs to. Here, EQL means equalization of the bit line and the sense amplifier based on the preceding data access to the word line WL
1
. Thus, it always takes a fixed and long time to access a different word line in the same bank.
In general, as well known, a DRAM senses data by using a ratio of a cell capacitance and a bit line capacitance to each other. Therefore, it should be considered that a memory is configured to ensure a cell capacitance for sensing cell data and to provide a high-speed sense operation. It is preferable to make the number of cells belonging to a bit line connected to one sense amplifier as small as possible. And it is also preferable to reduce the number of cells connected to one word line in order to decrease RC delay time needed as a rise time and a fall time of a word line.
In other words, in view of the functional improvement of a memory, the size of a cell array comprising a plurality of memory cells cannot be so large. Therefore, it is preferable to divide a memory into a number of cell arrays.
In a design of a memory, sense amplifiers are shared by adjacent cell arrays. Thus, the area occupied by the sense amplifier becomes half the area when the sense amplifier is not being shared. Such a shared sense amplifier, however, enables only one of the adjacent cell arrays to use the same at a single access.
In recent years, there has been employed a UMA (Unified memory Architecture) in which a single memory is data-accessed by many elements. By employing a UMA, access to word lines has been changed frequently. As a result, according to the prior art, an unnecessary waiting time during data transfer often occurs. Therefore, such a conventional system needs an improvement for more efficient use of memory data.
BRIEF SUMMARY OF THE INVENTION
In view of the considerations described above, the present invention has been achieved. It is therefore an object of the invention to provide a high-speed cycle clock-synchronous memory and a memory system allowing effective data transfer, which realizes a word line access cycle faster than that in a conventional technique.
A first aspect of the present invention is a high-speed cycle clock-synchronous memory device comprising:
a plurality of cell arrays each including a plurality of memory cells;
a sense amplifier circuit section shared by the cell arrays;
a cell array control circuit to which row and column addresses are simultaneously inputted to designate an arbitrary memory cell in the memory cells and which independently controls an access operation to the plurality of cell arrays; and
an address structure of the plurality of cell arrays, on the basis of a change in specific bits between a first address and a second address when the first address obtained according to a first command is compared with the second address obtained according to a second command sent subsequent to the first command, by which the accesses according to the first and second commands can be judged to be accesses to the same cell array, accesses to neighboring cell arrays, or accesses to cell arrays which are far from each other can be determined.
A second aspect of the present invention is a high-speed cycle clock-synchronous memory device comprising:
a plurality of cell arrays each including a plurality of memory cells;
a sense amplifier shared by the cell arrays; and
a cell array control circuit to which row and column addresses are simultaneously inputted to designate an arbitrary memory cell in the memory cells and which independently controls an access operation to the plurality of cell arrays,
wherein the device has a burst access operating mode in which a signal for designating a cycle in which a command is obtained synchronously with a clock and instructing a timing at which a command which continuously maintains a predetermined level at least in a period before the half of the cycle of the clock is used, and
when an address of the head memory address is supplied, the subsequent addresses can be accessed.
A third aspect of the present invention is a high-speed cycle clock-synchronous memory system comprising:
a memory section having a plurality of cell arrays each including a plurality of memory cells and to which row and column addresses are simultaneously inputted to designate an arbitrary memory cell among the memory cells, wherein an access operation is independently controlled to the plurality of cell arrays; and
a memory controller po
Kuyama Hitoshi
Toda Haruki
Tsuchida Kenji
Banner & Witcoff , Ltd.
Elms Richard
Kabushiki Kaisha Toshiba
Nguyen Tuan T.
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