High speed current switch

Details High speed current switch High speed current switch

1999-09-13

2001-04-03

Ballato, Josie (Department: 2836)

Electrical transmission or interconnection systems

Switching systems

Condition responsive

C341S144000

Reexamination Certificate

active

06211583

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates in general to current switches and in particular to a high-speed current switch suitable for use in high speed electronic systems.
2. Description of the Related Art
In many electronic systems it is important to rapidly switch a current on or off, or to rapidly redirect the current. The faster the current is switched or redirected, the more ideal the behavior of the overall circuit which the switch is supporting. High speed current switching is useful in digital-to-analog converters (DACs) for high performance audio such as compact disc (CD) players and direct digital synthesizers used in communication base stations. Further, high speed current switching is useful in current-mode (or charge pump) phase locked loop (PLL) circuits to improve noise and spurs performance.
Historically, a simple series switch
10
as shown in
FIG. 1
was implemented using a single bipolar or field effect transistor to turn on and off a current source
12
. When the simple series switch
10
was in the open position, the current source
12
was forced to shut down, thereby drawing no current. When the simple series switch
10
was in the closed position, the current source
12
drew current. A drawback of the simple series switch
10
was that when the current source device was turned off it was slow to turn back on, thereby causing the simple series switch
10
to be unsuitable for use in high performance DACs and PLLs.
Various approaches have been tried to improve the high-speed performance of these current switches. One such approach used a differential switch
14
as shown in FIG.
2
. The differential switch
14
could be designed using metal oxide semiconductor field effect transistor (MOSFET), metal semiconductor field effect transistor (MESFET), or bipolar technology. The differential switch
14
of
FIG. 2
comprised a first transistor
16
and a second transistor
18
that acted as switches to steer a source current
20
between an output terminal
22
and an internal node
24
. An output current
26
would be either zero or the value of the source current
20
depending on the state of the control signal. Because the current was steered to the output, the current source
12
was always on. For this reason, the differential switch
14
was able to switch the output current
26
on arid off significantly faster than the simple series switch
10
, which forced the current source to shut down when the switch was opened.
The differential switch
14
shown in
FIG. 2
had limitations that slowed its operation. When on, FET or bipolar devices stored a charge inside the device in the inversion layer or in the space-charge region. The amount of charge is a function of the internal device capacitance and the terminal voltages of the device. For example, in a MOSFET the stored inversion layer charge is a function of the inversion layer capacitance, gate oxide capacitance, and the gate-source voltage (Vgs) and the drain-source voltage (Vds). In the differential switch
14
of
FIG. 2
, the voltage at the internal node
24
probably was different from the voltage at the output terminal
22
, and the amount of charge stored in the first transistor
16
was typically different than that in the second transistor
18
. When the differential switch
14
changed state, the difference in charge must be transferred from parasitic capacitance in the circuit, and this modulated the voltage at a tail node
28
. This modulation of the voltage of the tail node
28
caused the output switch Vgs to vary, slowing the process of turning the device on and settling the output current
26
. In addition, variations in the voltage at the tail node
28
and any charge drawn from the output terminal
22
would create a spike of current at the output terminal
22
that took some time to settle. Part of this current spike was the charge difference needed for storage when the second transistor
18
was on. The current spike developed at the output terminal
22
increased the settle time of the output current
26
and could degrade the performance of the overall circuit that the current source
12
was supporting.
Recently, the limitations of the differential switch
14
have been improved on by forcing the voltage at the output terminal
22
and the voltage at the internal node
24
to be equal. When the first transistor
16
and the second transistor
18
are on, the charge differences are minimized and the switch will react more rapidly. One method of forcing the two terminal voltages to be equal is described in an article by Howard C. Yang, et al., entitled “A Low Jitter 0.3-165 MHz CMOS PLL Frequency Synthesizer for 3V/5V Operation”,
IEEE Journal of Solid State Circuits,
V32, N4, pp.582-586, April 1997.
A balanced current switch
30
as described in the Yang et al. article is reproduced in FIG.
3
. The reference numbers of the differential switch
14
of
FIG. 2
have been retained for those elements that are common. The balanced current switch
30
of
FIG. 3
includes all the elements and functionality of the differential switch
14
illustrated in FIG.
2
and further comprises an operational amplifier (op-amp)
32
. In the balanced current switch
30
, the op-amp
32
is connected in a unity-gain buffer configuration such that it forces the voltage at the internal node
24
to track the voltage at the output terminal
22
. Because the terminal voltages of the first transistor
16
and the second transistor
18
are equalized, the charge stored in each transistor (when each is on) is equalized as well. This significantly reduces the amount of charge that is drawn from parasitic capacitance in the circuit, and from the output node or the tail node, improving the settle time of the switch.
Although possessing improved performance over the differential switch
14
, the balanced current switch
30
still has drawbacks. The primary drawback of the balanced current switch
30
is that the op-amp output current
34
must rapidly switch between the source current
20
and zero when the current is steered to the output. Thus, the bandwidth and slew rate of the op-amp
32
constrains the reaction time of the feedback system, and therefore, the speed of the balanced current switch
30
. An additional drawback of the balanced current switch
30
is that the op-amp
32
must be able to source a current equal to the source current
20
, which can be quite large. This makes the op-amp design problem very difficult. The op-amp is required to simultaneously meet large output current and wide bandwidth and high slew rate constraints. The high performance op-amp required to meet these specifications would typically consume high current drain, be significantly large in size, and thus costly, which are undesirable in battery operated, portable products.
Despite the development of techniques such as those described previously above, a need still remains for improving the performance of high-speed current switches without the use of high performance operational amplifiers.


REFERENCES:
patent: 5136293 (1992-08-01), Matsuo et al.
patent: 5329192 (1994-07-01), Wu et al.
patent: 5373294 (1994-12-01), Sun
patent: 5463394 (1995-10-01), Sun
patent: 5548288 (1996-08-01), Lueng
patent: 5965958 (1999-10-01), Harwood
patent: 6100738 (2000-08-01), Illegems

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