Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
2000-02-22
2003-03-18
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S219000, C327S222000
Reexamination Certificate
active
06535042
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to latch circuits. More specifically, this invention relates to latches that have significantly reduced turn-ON and turn-OFF times.
FIG. 1
shows a conventional latch
100
formed by a cross-coupled pair of transistors, transistors
120
and
130
. Hereafter, the term cross-coupled transistors is used herein to refer to two transistors wherein the base of one is connected to the collector-emitter circuit of the other. Two additional transistors, transistors
110
and
140
, are coupled to the SET
190
and RESET
195
inputs of the circuit, and are labeled SET and RESET because they are used to trigger changes in the output state of latch
100
. Transistors
110
,
120
,
130
and
140
may each include a shottky diode, such as shottky diode
145
, across their respective collector/base junctions to prevent saturation, but only shottky diode
145
is shown to simplify the drawing.
The following is an exemplary truth table for the operation of the latch in FIG.
1
:
RESET
SET
Q
n+1
A
0
0
Q
n
B
0
1
1
C
1
0
0
D
1
1
not used
The outputs are labeled Q
170
and {overscore (Q)}
180
. These outputs are complementary—i.e., when Q
170
is high, {overscore (Q)}
180
is low and vice versa.
Latch
100
is considered SET when Q
170
is high and {overscore (Q)}
180
is low. It is RESET when Q
170
is low and {overscore (Q)}
180
is high. The operation of transistors
110
,
120
,
130
and
140
to produce the results found in the truth table above is well known.
One potential problem exists, however, with this circuit, as follows.
In normal storage operation, i.e., the state where both inputs SET
190
and RESET
195
are held close to ground, the outputs, Q
170
and {overscore (Q)}
180
, retain their previous state. This operation is shown in state A in the table above. In this state, the base of the SET and RESET transistors, transistors
110
and
140
respectively, are also held close to ground by SET
190
and RESET
195
inputs. To change the latch state, the base of one of transistors
110
and
140
must be pulled up by at least a V
be
(approximately 700 millivolts) in order to turn the transistor ON and are, therefore, voltage-driven—i.e., require a significant change in voltage to turn ON. This substantial difference in voltage required to alter the output value of the latch causes a delay because of the time constant associated with charging the base capacitance of the SET or RESET transistors with the full V
be
voltage and charging the base capacitance of the device driving the base of the SET or RESET transistors with the full V
be
voltage. The delay slows the operation of the latch. This problem is particularly relevant when the drive to the SET or RESET transistors is from the collector of a PNP.
There are several ECL (emitter-coupled logic) type latches that are commonly used to overcome this problem. They provide a solution by operating all the transistors in the active region and not in the saturated region. This reduces turn-OFF and turn-ON times because the transistors are not being fully charged and fully drained for each state change of the latch. However, these latches tend to be more complex than common latches and require input/output level shifting.
Therefore, it would be desirable to provide a simple latch that changes state in a substantially reduced time period.
SUMMARY OF THE INVENTION
Therefore, it is an object of this invention to provide a simple latch that changes state in a substantially reduced time period.
A latch circuit having at least one output and conducting a current is provided. A number of individual current sources may be utilized to produce the current. The latch circuit also includes a SET circuit and a RESET circuit. The SET circuit may include a first transistor and a SET transistor. The RESET circuit may include a second transistor and a RESET transistor. The first and second transistors may be cross-coupled to one another such that the base of one of the transistors is coupled to the collector-emitter circuit of the other. The SET transistor and the RESET transistor may receive a control signal at their respective bases to trigger the latch circuit to change output state. The latch circuit has at least two distinct output states. The SET transistor and the RESET transistor are coupled to the first and second transistors such that a small control signal supplied to one of the SET and RESET transistors varies the output of the latch between a first state and a second state. At the first output state of a latch according to the invention, the current may be conducted by the first transistor and the SET transistor, and at the second state, the current may be conducted by the second transistor and RESET transistor.
A latch circuit according to the invention reduces switching time because it maintains at least one of the SET and RESET transistors in a condition that is very close to triggering the latch circuit to change output state. This condition allows a small input signal to trigger the SET and RESET transistors to change the output state of the latch.
BRIEF DESCRIPTION OF THE DRAWINGS
The above and other objects and advantages of the invention will be apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which like reference characters refer to like parts throughout.
FIG. 1
is a circuit diagram of a conventional latch circuit.
FIG. 2
is a circuit diagram of a latch circuit according to the principles of the invention.
FIG. 3
is a circuit diagram of an alternate latch circuit according to the principles of the invention.
FIG. 4
is a circuit diagram of a PNP latch circuit according to the principles of the invention.
FIG. 5
is a circuit diagram of an oscillator circuit according to the principles of the invention.
FIG. 6
is a circuit diagram of a temperature-compensated oscillator circuit according to the principles of the invention.
FIG. 7
is a circuit diagram of an alternate latch circuit according to the principles of the invention.
FIG. 8
is a circuit diagram of an alternate latch circuit according to the principles of the invention.
REFERENCES:
patent: 5541544 (1996-07-01), Nakano
patent: 5604456 (1997-02-01), Nitta
Aldridge Jeffrey C.
Fish & Neave
Linear Technology Corporation
Nguyen Hiep
Weiss Joel
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