Multiplex communications – Pathfinding or routing – Through a circuit switch
Reexamination Certificate
2002-01-14
2004-03-02
Cangialosi, Salvatore (Department: 2661)
Multiplex communications
Pathfinding or routing
Through a circuit switch
C370S367000
Reexamination Certificate
active
06700886
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to high speed data communication network systems and, more particularly, to a bit and word synchronized high speed serial switch routing system.
BACKGROUND OF THE INVENTION
Modern, high-speed data communication and transmission frequently involves the use of multiple transmitters and receivers communicating with one another, or with multiple memory devices, for example, over high-speed data transmission lines. Such high-speed data transmission generally imposes stringent requirements on clock synchronization. Further, high speed data communication systems require large amounts of data to be sent to various different locations or devices comprising a communication network. This is typically performed by using networking devices, conventionally termed switches or routers, which receive data from a particular transmitter and reconfigure a signal path in order to send the data to a designated recipient. Conventional switches or routers implement a “switch fabric” using integrated circuits to provide a data route from a receiving input port to a correct output port of the networking device (the switch). The data routes often implemented in high-speed switch fabrics are generally one bit wide. Thus, for such switches the switch fabric routes data over a plurality of serial data paths.
Modern high-speed communication systems place inordinate demands upon the performance requirements of the switch of a network switching system. The switch must be able to operate at a sufficiently high bandwidth such that signal processing is not unduly delayed while data is being transferred. Further, connections are frequently being made and broken, such that delays often occur while waiting for a connection. In addition, the various possible routes through the switch fabric from one port to another port are not always of equal length. Therefore, signal path lengths, and signal delays, change with each reconfiguration of the switch.
FIG. 1
illustrates a prior art semi-schematic simplified block diagram of a network switching system. As illustrated in
FIG. 1
a crosspoint switch or router circuit is typically implemented as a number of integrated circuit components configured on a printed circuit board or card
10
. The switch need not be a crosspoint switch, delta or other switch types may also be used. The switch
10
comprises a switch matrix or fabric
12
which is reconfigurable under control of a central processing unit
14
to receive data from a switch port circuit
16
and route the data to a designated recipient switch port.
Data is transmitted to, and received from corresponding switch ports by a multiplicity of transceiver circuits
18
. The transceiver circuits are configured to move data to and from a particular user application through transmit and receive FIFOs over parallel interface busses. Parallel data is serialized and directed to a particular switch port over a high-speed serial interface. Likewise, serial data is received by the transceiver
18
from a corresponding switch port
16
. The transceiver deserializes the serial data and interfaces with a user application circuit through a receive FIFO over a parallel data bus.
Each of the transceivers
18
typically include a clock and data recovery circuit (CDR)
20
. The CDR locks onto the incoming serial data stream in order to recover clock information suitable for controlling the timing of the various registers comprising the transceiver. As noted above, when control signals to the crosspoint switch change the switch configuration, the delay through the crosspoint also changes. Because of this delay change, the CDR must realign itself to the phase of the new data stream.
In addition, prior art-type transceiver circuits are typically constructed with their own reference clock generator
22
. The reference clock generator functions as a frequency reference for the CDR
20
such that the CDR
20
is able to operate in “fly wheel” mode during periods when there is no data. Since reference clock generators may be frequency mismatched by approximately 100 PPM with respect to one another, it is possible that a serial bit stream developed by one transceiver and received by a second transceiver is sufficiently shifted in phase such that a certain number of bits might be lost in each transmitted frame. Moreover, during long periods of transmission from one transceiver to another data may be lost due to timing drift because the clocks of various transceivers may be of slightly different frequencies. This necessitates periodic switch reconfiguration to force transceiver resynchronization, with prior art switches usually having a cell period defining a maximum continuous transmission length. Each time transmission is interrupted to force resynchronization, of course, effective switch bandwidth is reduced. Further, variations due to transceiver frequency mismatch and the changing delay paths through a crosspoint matrix are random in direction as well as frequency. Adjusting a CDR in response to a serial data stream received from a first transceiver may result in over-correction, particularly if the serial data stream from a next transceiver is jittered in the other direction.
In addition, the crosspoint switch delay change caused by reconfiguration can be larger than one bit time, such that word or frame realignment must also be performed by the receiving transceiver. Word or frame realignment is a generally lengthy process requiring many bit times to perform. Thus, a dead period is induced in the data stream which contains no valid data. In asynchronous transmission mode switches, for example, this realignment dead period reduces the effective bandwidth of a network switching system by approximately 10-20%. Moreover, phase recovery circuitry must be made as fast as possible to compensate for transceiver frequency mismatch and to minimize realignment induced dead time. Conventional systems typically use up an additional 10-20% of bandwidth in order to provide a minimum number of transitions to guarantee that the serial data stream comprises a sufficiently high transition rate to support fast phase recovery circuits.
Serial data transmission may also be synchronous. In synchronous data transmission the sequence of binary “ones” and “zeros”, making up the data stream, occurs with reference to a data bit cell defined by a uniform or single-frequency clock signal transmitted with the data. Transmitting the clock signal together with the data, however takes up valuable bandwidth, increases high speed line requirements, and reduces the data transmission capability of the system. In addition, word alignment must still be performed.
The effects of jitter, or bit shift, in a serial data stream are illustrated in FIG.
2
. Data has been phase-locked to a bit clock signal wherein data is stable within a particular bit period such that it may be strobed into an input register on the falling edge of bit clock. Given perfect phase and frequency lock, the periodicity of the bit clock signal might serve to define synchronous bit cells; a logical high data occurring within a code bit cell representing a logic ONE, a logical zero on data occurring within a code bit cell representing a logic zero. The data sequence illustrated would therefore be read as 11011000.
Phase jitter, frequency mismatch, and/or a delay change through the switch matrix, has displaced, or shifted, the serial data stream by approximately 90 degrees in phase. Data stability, of the late data stream, occurs outside of the intended code bit cell, and into the next code bit cell, causing the data stream sequence to be incorrectly read as 01101100 rather than 11011000. Thus, it can be seen that by merely shifting a particular serial data stream by approximately 90 degrees in phase, the binary sequence comprising a data word, as represented within a frame defined by a word clock signal, causes the word to lose all meaning.
The random nature of data shift can be appreciated by referring to FIG.
3
. Shifts in the nominal position of a data
Lee Gary M.
Mullaney John P.
Cangialosi Salvatore
Christie Parker & Hale LLP
Vitesse Semiconductor Corporation
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