High speed concurrent testing of dynamic read/write memory array

Details High speed concurrent testing of dynamic read/write memory array High speed concurrent testing of dynamic read/write memory array

1988-01-15

1989-09-19

Fleming, Michael R.

Excavating

365201, G06F 1110

Patent

active

048688231

ABSTRACT:
A semiconductor read/write memory device has a normal mode of operation and a test mode. The test mode allows concurrent writing to a number of cells in the cell array so that test patterns may be rapidly loaded. The cell array is split into subarrays and the column addressing circuitry is arranged to provide a maximum of spacing between the cells that are concurrently written. In this manner, pattern sensitivity tests may be run at higher speed because a number of bits at widely spaced positions in the array can be tested simultaneously.

REFERENCES:
patent: 4654849 (1987-03-01), White
patent: 4656610 (1987-04-01), Yoshida
patent: 4692901 (1987-09-01), Kumanioya
patent: 4715034 (1987-12-01), Jacobson
patent: 4719411 (1988-01-01), Buehlar
patent: 4730320 (1988-03-01), Hidaka
patent: 4739250 (1988-04-01), Tanizawa
patent: 4742489 (1988-05-01), Hoffman
patent: 4744061 (1988-05-01), Takemas

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