High speed computer data transfer system

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

Patent

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Details

307443, 307452, 307480, 307481, 307351, 307362, 307546, 365203, 365205, H03K 19094, H03K 5153

Patent

active

049926780

ABSTRACT:
A high speed computer data transfer system includes a clamping circuit for limiting pre-charge voltages in the case where multiple pre-charge cycles occur before a pull-down operation. Data bus voltage swings between logic high and logic low levels as well as pull-down times are reduced, thus lowering the time needed to transfer the data. The preferred embodiment is implemented using complementary metal-oxide-semiconductor (CMOS) technology.

REFERENCES:
patent: 4488066 (1984-12-01), Shoji
patent: 4498021 (1985-02-01), Uya
patent: 4572972 (1986-02-01), Shoji
patent: 4598216 (1986-07-01), Lauffer et al.
patent: 4670666 (1987-06-01), Yoshida
patent: 4761567 (1988-08-01), Walters, Jr. et al.
patent: 4763023 (1988-08-01), Spence
patent: 4772888 (1988-09-01), Kimura

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