Active solid-state devices (e.g. – transistors – solid-state diode – Schottky barrier – To compound semiconductor
Reexamination Certificate
2001-07-17
2003-07-01
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Schottky barrier
To compound semiconductor
C257S471000, C257S192000
Reexamination Certificate
active
06586813
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
The present application is based on Japanese priority application No.2000-216387 filed on Jul. 17, 2000, the entire contents of which are hereby incorporated by reference.
BACKGROUND OF THE INVENTION
The present invention generally relates to semiconductor devices and more particularly to a high-power and high-speed semiconductor device.
With widespread use of mobile telecommunication technology, there is a demand for high-power and high-speed semiconductor devices for use in base stations as final stage amplifiers, and the like.
Conventionally, high-power semiconductor devices have been realized by increasing the gate width so as to increase the drive current. However, such an approach has a drawback, associated with the increased output current, of large power loss occurring in an impedance matching circuit that is used in combination with the semiconductor device. In view of this problem, recent high-power semiconductor devices achieve the desired increase of output power by increasing the operating voltage.
FIG. 1
shows the construction of a conventional high-power, high-speed semiconductor device
10
.
Referring to
FIG. 1
, the semiconductor device
10
is a MESFET formed on a semi-insulating GaAs substrate
11
, and includes a buffer layer
11
A of undoped GaAs formed on the GaAs substrate
11
, a channel layer
12
of n-type GaAs formed on the buffer layer
11
A, a Schottky contact layer
13
of undoped AlGaAs formed on the channel layer
12
, and a cap layer
14
of undoped GaAs formed on the Schottky contact layer
13
. Further, a gate electrode
15
makes a Schottky contact with the Schottky contact layer
13
in a gate recess structure formed in the cap layer
14
, and n+-type diffusion regions
16
and
17
are formed at respective sides of the gate electrode
15
with a separation therefrom. Each of the diffusion regions
16
and
17
extends from the cap layer
14
to the buffer layer
11
A and forms a source region or a drain region. Further, a source electrode
16
A is formed on the source region
16
in ohmic contact therewith, and a drain region
17
A is formed on the drain region
17
also in ohmic contact therewith.
In the MESFET
10
of
FIG. 1
, the exposed part of the cap layer
14
is covered by a passivation film
18
of SiN.
In the case the MESFET
10
is driven so as to provide large output power, it is necessary to apply a large voltage between the gate electrode
15
and the drain electrode
17
A.
On the other hand, the use of such a large operational voltage tends to cause the problem of excessive electric field strength in the channel region formed underneath the gate electrode
15
, particularly in the vicinity of the drain edge. The large electric field thus induced in the vicinity of the drain edge may cause the problem of avalanche breakdown in the channel region as represented in FIG.
2
. When this occurs, a large gate leak current is caused to flow along a path (
1
) as represented in
FIG. 2
, and the desired high-power operation of the MESFET
10
becomes no longer possible.
Further, there may exist another leakage current path (
2
) in the conventional MESFET
10
of
FIG. 1
as represented in
FIG. 2
, although the magnitude of the leakage current along the path (
1
) is larger than the leakage current along the path (
2
) by the factor of ten or more.
In order to avoid the problem of gate leakage current, it has been practiced conventionally to increase the distance between the gate electrode
15
and the drain electrode
17
A so as to reduce the electric field strength right underneath the gate electrode in the pinch-off mode. According to this approach, it is confirmed that there occurs a desired increase of the gate-drain breakdown voltage and also a desired decrease of the gate leakage current.
On the other hand, the foregoing conventional approach still has a drawback in that, while it can successfully increase the gate-drain breakdown voltage, there also occurs an increase of the source-drain resistance, resulting in a decrease of the maximum output current, and hence a decrease of maximum output power that can be taken out from the semiconductor device. Further, the approach of increasing the gate-drain distance tends to cause the problem of Gunn oscillation.
From the reasons noted before, it will be understood that there exists an inherent limitation in the foregoing conventional approach for realizing high-power operation of MESFET
10
of FIG.
1
.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide a novel and useful semiconductor device wherein the foregoing problems are eliminated.
Another and more specific object of the present invention is to provide a high-speed compound semiconductor device capable of providing large output power.
Another object of the present invention is to provide a high-speed compound semiconductor device operable at large output power with minimized leakage current.
Another object of the present invention is to provide a compound semiconductor device, comprising:
a substrate;
a channel layer formed on said substrate;
a cap layer formed on said channel layer;
an insulating film formed on said cap layer;
a gate recess opening penetrating through said insulating film and said cap layer;
an n-type source region extending from a surface of said cap layer and reaching said channel layer at a first side of said gate electrode;
an n-type drain region extending from a surface of said cap layer and reaching said channel layer at a second side of said gate electrode;
a source electrode contacting with said source region electrically; and
a drain electrode contacting with said drain region electrically,
said gate electrode having a &Ggr; shape and extending over said insulating film from said gate recess opening in a direction of said second side,
a total thickness of said insulating film and said cap layer being set such that there is formed an electric field right underneath an extending part of said gate electrode such that said electric field has a component acting in a direction perpendicular to a principal surface of said substrate with a substantial magnitude.
According to the present invention, it becomes possible to improve the gate breakdown characteristics of a high-speed field-effect semiconductor device by providing thereto a &Ggr;-shaped gate electrode and by optimizing the thicknesses of the passivation film and the cap layer such that the shape of the gate electrode can deform the potential distribution profile in the vicinity of the drain edge. As a result of the present invention, it becomes possible to use a large gate-drain voltage and the semiconductor device can be driven so as to provide a large output power.
Other objects and further features of the present invention will become apparent from the following detailed description when read in conjunction with the attached drawings.
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patent: 4889831 (1989-12-01), Ishii et al.
patent: 4916498 (1990-04-01), Berenz
patent: 5023674 (1991-06-01), Hikosaka et al.
patent: 5374835 (1994-12-01), Shimada et al.
patent: 6294801 (2001-09-01), Inokuchi et al.
patent: 5-326563 (1993-12-01), None
Li et al., “High breakdown voltage GaN HFET with field plate,” Electronics Letters, Feb. 1, 2001, vol. 37, No. 3, p. 196-197.*
C.L. Chen et al., IEEE Electron Device Letters 13, No. 6, New York, Jun. 1992.
N. -Q. Zhang et al.; Extended Abstract of the 1999 International Conference on Solid State Devices and Materials; pp. 212-213, Tokyo, 1999.
Armstrong Westerman & Hattori, LLP
Flynn Nathan J.
Fujitsu Quantum Devices Limited
Quinto Kevin
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