High-speed complementary multiplexer

Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Converging with plural inputs and single output

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327362, H03K 1756

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active

053768299

ABSTRACT:
The complementary multiplexer includes a first pass-gate, formed from a single PMOS transistor, and a second pass-gate formed from a single NMOS transistor. The gates of the PMOS and NMOS transistors are connected directly to a select input line. No inversion of the select input signal is required. A compensation circuit is connected to outputs of the pass-gates for compensating any voltage differences between signals received through the first pass-gate as opposed to those received through the second pass-gate. Full CMOS and bi-CMOS implementations are described herein. An exclusive OR-gate circuit, incorporating a bi-CMOS implementation of the multiplexer, is also described herein.

REFERENCES:
patent: 3739193 (1973-06-01), Pryor
patent: 4424460 (1984-01-01), Best
patent: 4567385 (1986-01-01), Falater et al.
patent: 5070255 (1991-12-01), Shin
patent: 5111077 (1992-05-01), Young et al.
patent: 5113096 (1992-05-01), Lev et al.
patent: 5155387 (1992-10-01), Fletcher et al.
patent: 5162666 (1992-11-01), Tran
patent: 5233233 (1993-08-01), Inoue et al.
IBM Technical Disclosure Bulletin, vol. 24, No. 4, Sep. 1981.

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