High speed complementary flipflop

Details High speed complementary flipflop High speed complementary flipflop

1990-11-06

1991-09-17

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072722, 307452, 307480, H03K 1153

Patent

active

050497600

ABSTRACT:
A complementary flipflop circuit is provided combining high speed with substantially zero DC current flow in standby mode between clock signal transitions. A differential input stage having n-channel transistors is gated by one phase of a clock signal for storing a complementary data input signal at the drains of p-channel load transistors which are cross-coupled to the first and second outputs of the differential input stage. The zero DC current flow is provided as the complementary configuration of the p-channel load transistors and the n-channel transistors of the differential input stage maintains isolation between the power supply conductors between transitions of the clock signal thereby reducing the average power consumption. The high operation bandwidth is achieved by using only a single p-channel transistor between the power supply conductors with gallium arsenide material.

REFERENCES:
patent: 4512029 (1985-04-01), Brice
patent: 4656371 (1987-04-01), Binet et al.

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