Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1989-10-31
1991-07-16
Zazworsky, John
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
307494, 307355, 307530, 307279, H03K 3356, H03K 3023
Patent
active
050327445
ABSTRACT:
A regenerative latch includes a fully differential amplifier with two inputs and two outputs and two positive feedback paths, each path coupling each of the two outputs to one of the two inputs through a capacitor. Hence, during the reset phase, the two capacitors will block all DC voltages thereby enabling offset cancellation of the amplifier. During the regeneration phase, the two positive feedback paths drive the amplifier quickly into saturation. The output of the regenerative latch may be used to drive a second stage latch to reduce metastability and to reduce the gain requirements for the latch. The transistor channels of the input transistors of the second stage latch are reverse biased into depletion regions to reduce the input capacitance of the second latch during reset. Such low input capacitance speeds up the regeneration of the first stage latch.
REFERENCES:
patent: 4629911 (1986-12-01), Bebernes et al.
patent: 4802130 (1989-01-01), Soneda
patent: 4814642 (1989-03-01), Kleks
patent: 4858195 (1989-08-01), Soneda
Wu and Wooley, "A 100-MHz Pipelined CMOS Comparator", IEEE Journ. of Solid-State Circuits, vol. 26, 23:1379-1385 (Dec. 1988).
McCreary and Gray, "All-MOS Charge Redistribution Analog-to-Digital Conversion . . . ", IEEE Journ. of Sol.-Sta. Circuits, V.SC-10, pp. 371-379, No. 6, Dec. 1975.
Yee, Terman and Heller, "A 1 mV MOS Comparator", IEEE Journ. of Solid-State Circuits, V1., SC-13, No. 3, pp. 294-297 (Jun. 1978).
Poujois and Borel, "A Low Drift Fully Integrated MOSFET Operational Amplifier", IEEE Journ. of Solid-State Circuits, V1., SC-13, pp. 499-503.
Yukawa, "A CMOS 8-Bit High Speed A/D Converter IC", IEEE Journ. of Solid-State Circuits, V., SC-20, No. 3, pp. 775-779 (Jun. 1985).
Lee, Hodges and Gray, "A Self-Calibrating 15 Bit CMOS A/D, Converter", IEEE Journ. of Solid-State Circuits, V.SC-19, No. 6, pp. 813-819.
VLSI Technology Inc.
Zazworsky John
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