High-speed comparator logic for wide compares in programmable lo

Details High-speed comparator logic for wide compares in programmable lo High-speed comparator logic for wide compares in programmable lo

1993-02-16

1994-04-12

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3401462, 364716, H03K 19173, G06F 738

Patent

active

053028651

ABSTRACT:
A programmable gate array comprised of a number of configurable functional blocks. Each configurable functional block has a number (m) of inputs. A global interconnect matrix interconnects the configurable functional blocks. The global interconnect matrix provides for routing any combination of signals entering the matrix to any configurable functional block, up to and including the maximum number (m) of inputs of a configurable functional block. Each configurable functional block includes a product term array connected to the m inputs. The product term array can perform a logical AND of up to m bits. A compare term array is also connected to the m inputs. The compare term array can perform an identity compare of up to m/2 bits. A number n of macro cells are provided in each configurable functional block wherein the number n is less that the number m. An allocation circuit allocates the outputs of the compare term array and the product terms to a macro cell, any compare term being allocable in place of a product term to the macro cell.

REFERENCES:
patent: 4348737 (1982-09-01), Cakier et al.
patent: 4536738 (1985-08-01), Huse et al.
patent: 4799152 (1989-01-01), Chuang et al.
patent: 5059942 (1991-10-01), Burrows
patent: 5224072 (1993-06-01), Matsubara

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