High speed comparator

Details High speed comparator High speed comparator

1999-02-22

2001-01-23

Wambach, Margaret R. (Department: 2816)

Communications: electrical

Digital comparator systems

Reexamination Certificate

active

06177862

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention generally relates to a comparator, and, more particularly, to speed improvements in a bit data comparator.
Comparators have many uses in electronic devices. For example, in order to check an access address to a memory device, a comparator for comparing two address data signals is used. In general, the comparator includes XOR circuits and a logic circuit connected to the XOR circuits. Each XOR circuit detects the coincidence of each data bit. When the two bits coincide, a signal having a logical value of “0” (L level) is output, and when the two bits do not coincide, a signal having a logical value of “1” (H level) is output. The logic circuit receives the output signals from the XOR circuits and determines the coincidence of the two address signals based on whether the logical value of each signal is 0. The logic circuit may be, for example, an n-input NAND circuit.
The n-input NAND circuit includes a number n of pMOS transistors connected in parallel to a power supply and a number n of nMOS transistors connected in series between the pMOS transistors and ground. The output signal of the NAND circuit is obtained from the node between the pMOS transistors and the uppermost stage nMOS transistor. However, since the nMOS transistors are connected in series, the next stage nMOS transistor turns on only when the nMOS transistor near the power supply turns on. Accordingly, the operating speed of the NAND circuit is quite slow.
FIG. 1
is a block diagram of a conventional comparator
10
. The comparator
10
compares two 12-bit data words A
11
to A
0
and B
11
to B
0
. The comparator
10
includes twelve XOR circuits
11
A to
11
L (only eight XOR circuits are illustrated), three 4-input NOR circuits
12
A to
12
C (only two NOR circuits are illustrated), one 4-input NAND circuit
13
, and an inverter
14
.
The XOR circuits
11
A to
11
L receive the data bits A
0
to A
11
and the data bits B
0
to B
11
, respectively. When two compared bits coincide, a signal having the logical L level is output, and when the two bits do not coincide, a signal having the logical H level is output.
The 4-input NOR circuit
12
A receives the output signals from the XOR circuits
11
A to
11
D. The 4-input NOR circuit
12
B receives the output signals from the XOR circuits
11
E to
11
H. The 4-input NOR circuit
12
C receives the output signals from the XOR circuits
11
I to
11
L. Each of the 4-input NOR circuits
12
A to
12
C outputs a signal having the logical L level when any one of the four input signals has the logical H level.
The 4-input NAND circuit
13
receives the output signals from the three 4-input NOR circuits
12
A to
12
C and outputs an output signal in accordance with a control signal CS. For example, when the control signal CS has the logical H level and all of the output signals from the 4-input NOR circuits
12
A to
12
C have the logical H levels, the NAND circuit
13
outputs an output signal having the logical L level and the inverter
14
outputs an output signal OUT having the logical H level. In other words, when the two data words coincide and the control signal is high, the NAND circuit
13
outputs a signal having the logical L level.
However, because the comparator
10
has a 2-stage configuration, it does not operate at a very high speed. In particular, as the number of data bits increases, the circuit configuration exceeds 2-stages, so that the operating speed becomes even slower.
Further, in principle, the NOR circuit includes n number of pMOS transistors connected in series to the power supply and n number of nMOS transistors connected in parallel between the pMOS transistors and a ground. Accordingly, as the number of the input signal increases, for example by one, an additional pMOS transistor and an additional nMOS transistor become necessary. As a result, the number of elements increases and the circuit area increases.
It is an object of the present invention to provide a comparator that is relatively fast and does not require an increased elements to compare more data bits.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a comparator is provided that includes a plurality of coincidence detection circuits for comparing first bit data and second bit data and generating a plurality of detection signals that indicate a coincidence detection result for each bit. A decision circuit receives the plurality of detection signals and generates a decision signal indicating the coincidence decision results of the first and second bit data. The decision circuit includes a plurality of switching circuits that operate in parallel in response to the plurality of detection signals, respectively, to generate the decision signal.
In another aspect of the present invention, a comparator is provided that includes a plurality of coincidence detection circuits for comparing first bit data and second bit data and generating a plurality of detection signals that indicate a coincidence detection result for each bit. A first inverter circuit receives a first control signal and outputs an inverse signal of the first control signal from an output terminal thereof. A plurality of switching circuits are connected in parallel between the output terminal of the first inverter circuit and ground and receives the plurality of detection signals and generates a decision output signal.
In yet another aspect of the present invention, a comparator is provided that compares a first data word with a second data word. The comparator includes a plurality of two input XOR gates. Each of the XOR gates receives one bit of the first word and a corresponding bit of the second word and outputs a coincidence detection signal. A first inverter circuit receives a control signal and generates an inverted control signal. A decision circuit receives the inverted control signal from the first inverter circuit and receives each of the coincidence detection signals from the plurality of XOR gates, and generates a decision circuit output signal. The decision circuit includes a second inverter circuit has an input terminal connected to the output of the first inverter circuit and receives the inverted control signal, and an output terminal. The output terminal forms a first node. A plurality of transistors are connected in parallel between the first node and ground. The gates of the transistors receive the respective coincidence detection signals. A two input NAND gate receives the decision circuit output signal and the control signal and generates a comparator output signal.
Other aspects and advantages of the invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.


REFERENCES:
patent: 5471189 (1995-11-01), Dietz et al.
patent: 5592142 (1997-01-01), Adams et al.

Affiliated with

Also associated with

Rating

High speed comparator does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High speed comparator, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High speed comparator will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2542947