Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
2000-05-18
2001-11-27
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S196000, C327S218000, C326S134000, C326S135000, C377S128000
Reexamination Certificate
active
06323709
ABSTRACT:
TECHNICAL FIELD
This invention relates to edge-triggered flip-flop circuits.
BACKGROUND ART
Flip-flop circuits are essential components in any digital system design and are used in almost all integrated circuits that are manufactured. Flip-flop circuits are normally used to store data that is a result of a computation performed by a digital circuit or they are used to sequence data in an integrated circuit in order to facilitate some manner of computation.
Binary flip-flops are flip-flop circuits that store two possible signal levels, logic low and logic high. All signals that are applied to the flip-flop circuits can be considered to have the aforementioned two possible logic levels.
There are two distinct approaches to such conventional flip-flop design. The first approach uses gate-level design i.e. individual functional logic gates such as NAND, NOR, AND, OR or INVERSION are used to achieve edge-triggering effect. These solutions are static gates and have high device count as well as low speed of operation. They are, however, very reliable and robust.
The second approach uses a dynamic or pseudo-static flip-flop implementation. These are more compact and faster implementations of a flip-flop as compared to the static approach. However, the dynamic nature of these circuits makes them less reliable. The latter approach to flip-flop design, however, is most prevalent in state-of-the-art ICs that constantly aim to push circuit operation at greater speeds.
One important characteristic of edge-triggered flip-flop circuits is that data presented at the input of the circuit or as determined by the flip-flop control signals such as S-R or T is reflected at the output of the circuit either on the low-to-high transition (positive edge-trigger) or the high-to-low (negative edge-trigger) transition of a clocking signal.
In general, the ideal behavior of a flip-flop circuit would be to act as a storage element but not introduce additional delay in the signal path in which the flip flop is inserted, and to not consume any circuit area in doing so. It is well known that the real life behavior of flip-flop circuits is non-ideal as a result of which flip-flop circuits do cause delay and area overhead in integrated circuits. Thus, one of the objectives of a flip-flop design is to reduce its delay and area. Also, the non-ideal behavior of flip-flop circuits dictates that the input signals to the flip-flop be held a constant value for a small window around the edge of the clocking signal. It is also a criterion of flip-flop circuit design to reduce this window to a very small fraction of the total period of the clocking signal.
NDR diodes such as resonant tunneling diodes (RTDs) have been used to design high-speed and compact digital logic circuits due to their picosecond switching speeds and folded current vs. voltage characteristics. While latching storage circuits can be built efficiently due to the inherent bistability in the NDR diode characteristics, such circuits use level-sensitive clocking signals, i.e. any change in the input when the clocking signal is active (be it high or low) is reflected at the output. Thus, in order for the circuit to function correctly, input data must be maintained for the entire duration of the active portion of the clocking signal and not just in a small window around the active transition edge of the clocking signal.
The time period for which the data needs to be constant before the active clock edge is called the setup time and the time period for which the data needs to be held constant after the active clock edge is called the hold time. There are no known implementations of edge-triggered flip-flop circuits using NDR diodes.
Prior art U.S. patents, generally relevant the present invention include: U.S. Pat. Nos. 4,057,741; 4,140,924; 4,656,368; and 5,189,315.
A prior art article also generally relevant to the present invention is: J. Yuan and C. Svensson, “High-Speed CMOS Circuit Technique”, IEEE
JOURNAL
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OLID
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TATE
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IRCUITS
, Vol. 24, No. 1, February 1989, pp. 62-70.
DISCLOSURE OF INVENTION
An object of the present invention is it provides a high-speed, compact, edge-triggered, flip-flop circuit.
Another object of the present invention is it provides a high-speed, compact, edge-triggered, flip-flop circuit which also has improved reliability.
Yet another object of the present invention is it provides a high-speed, compact, edge-triggered, flip-flop circuit which more closely approximates the ideal behavior of a flip-flop circuit by reducing delay and area overhead on integrated circuits.
In carrying out the above objects and other objects of the present invention, a high-speed, compact, edge-triggered, flip-flop circuit includes an input circuit section having at least one input for receiving at least one input signal, a clock input for receiving a clock signal having two states and a data output. A latch circuit section has at least one semiconductor device which has negative differential resistance characteristics and is are connected to the data output of the input circuit section. An output circuit section has a data input connected to the at least one semiconductor device, a clock input for receiving the clock signal and a data output wherein a value is stored at the data output of the output circuit section in response to the at least one input signal when the clock signal makes a transition from one of its states to the other one of its states.
The circuit may be a D flip-flop circuit wherein the at least one input signal is a data input signal having a value and the value stored at the data output of the output circuit section has the value of the data input signal after the clock signal makes the transition.
The circuit may be a T flip-flop circuit wherein the at least one input signal may also be a toggle input signal to toggle the circuit when the clock signal makes the transition.
The circuit may be an S-R flip-flop circuit wherein the input circuit section has first and second inputs for receiving set or reset input signals, respectively, to set or reset the circuit when the clock signal makes the transition.
The circuit may further include an asynchronous preset circuit section for setting the data output of the output circuit section to a stable state without the necessity of receiving the clock signal, and an asynchronous reset circuit section for setting the data output of the output circuit section to a stable state without the necessity of receiving the clock signal.
The latch circuit section may include a plurality of semiconductor devices such as a pair of negative differential resistance diodes. The diodes may be series-connected resonant tunneling diodes.
The plurality of semiconductor devices may include a pair of negative differential resistance diodes having a folded-back, current-voltage characteristic.
The output circuit section may also have at least one semiconductor device having negative differential resistance characteristics and may be connected to the data output of the output circuit section.
The output circuit section may also include a plurality of semiconductor devices having negative differential resistance characteristics and may be connected to the data output of the output circuit section.
The circuit may include a pair of cascaded bistable NDR inverters which operate on opposite phases of the clock signal.
The circuit may also include a pair of cascaded bistable NDR latches which operate on opposite phases of the clock signal.
The circuit may further include a pair of cascaded pseudo-bistable latches which operate on the same phase of the clock signal.
The input circuit section may include a feedback circuit section connected to the data output of the output circuit section and the at least one input of the input circuit section.
The edge-triggered flip-flop circuit of one embodiment of the present invention, also referred to as a quantum metal oxide semiconductor (QMOS) flip-flop, comprises a circuit built using negative differential resistance (NDR) diodes and metal oxide semiconductor field e
Bhattacharya Mayukh
Kulkarni Shriram
Mazumder Pinaki
Brooks & Kushman P.C.
Lam Tuan T.
The Regents of the University of Michigan
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