Pulse or digital communications – Cable systems and components
Reexamination Certificate
1999-08-11
2004-08-10
Phu, Phoung (Department: 2731)
Pulse or digital communications
Cable systems and components
C375S219000, C375S354000, C710S061000
Reexamination Certificate
active
06775328
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a high-speed communication system and, more particularly, to a high-speed communication system with a feedback synchronization loop.
2. Description of the Related Art
A gigabit communication system is a system that transfers billions of bits of data per second between the nodes of the system. Gigabit communication systems commonly handle the data transferred over the backplane of the internet, and are expected to handle the data transferred between next-generation processors and peripherals, such as hard drives and printers.
FIG. 1
shows a block diagram that illustrates a conventional gigabit communication system
100
. As shown in
FIG. 1
, system
100
includes a high-speed transmission medium
108
, such as a fiber optic cable, and a number of communication devices
110
that receives data from, and transmits data to, medium
108
.
Each communication device
110
, in turn, includes a physical layer device
112
that is connected to medium
108
, and a processing device
114
that is connected to physical layer device
112
by a number of lines
116
. Physical layer device
112
includes a serializer/deserializer (serdes) that transforms data received from medium
108
into a signal format that is compatible with processing device
114
, and transforms data from processing device
114
into a signal format that is compatible with medium
108
.
When transferring data to, and receiving data from, processing circuit
114
, the serdes typically utilizes a data signal which has a logic high that is represented by a maximum voltage which is equal to the supply voltage used by the processing circuit.
For example, when device
114
is formed in a 0.35 micron photolithographic process, physical layer device
112
transmits data to, and receives data from, device
114
with data signals that have a maximum voltage of approximately 3.3V, the supply voltage commonly used with 0.35 micron devices.
One channel of data is typically transported across medium
108
, and between physical layer device
112
and processing device
114
, at 1.25 Gb/s, with speeds of 2.5 Gb/s under consideration. Processing device
114
processes the data received from medium
108
by physical layer device
112
, and outputs processed data to physical layer device
112
for transmission onto medium
108
.
Physical layer device
112
and processing device
114
are typically encapsulated in separate chips which are placed on the same printed circuit board due to the largely analog nature of device
112
and the largely digital nature of device
114
. One consequence of this approach, however, is that electromagnetic interference (EMI) requirements limit the maximum speed that data can be exchanged between devices
112
and
114
.
For example, when data is exchanged between devices
112
and
114
with data signals having a maximum voltage of approximately 3.3V, the maximum speed that can be obtained without exceeding the EMI requirements is approximately 125 Mb/s.
Thus, to handle one channel of inbound data, which is received at 1.25 Gb/s, 10 inbound lines
116
are required to transport data from device
112
to device
114
, where physical layer device
112
has 10 output ports and processing device
114
has 10 input ports. (10 inbound lines
116
at 125 Mb/s provide one channel of inbound data at 1.25 Gb/s).
Similarly, processing device
114
requires 10 outbound lines
116
to transport one channel of outbound data from device
114
to device
112
, where processing device
114
has 10 output ports and physical layer device
112
has 10 input ports. Thus, device
112
and
114
each require 20 input/output ports, with
20
corresponding pins, to handle the inbound and outbound data for one channel.
To provide additional EMI margin and greater chip-to-chip spacing, communication devices with reduced chip-to-chip speeds are also available. These reduced-speed devices typically transfer data between devices
112
and
114
at 62.5 Mb/s.
One problem with communication devices that have reduced chip-to-chip speeds, however, is that devices
112
and
114
have twice as many I/O ports and twice as many pins. Thus, with a reduced-speed device, devices
112
and
114
require 40 pins each (20 inbound lines
116
at 62.5 Mb/s are required to provide one input channel at 1.25 Gb/s, while 20 outbound lines
116
at 62.5 Mb/s are required to provide one outbound channel at 1.25 Gb/s).
The pin problem becomes even worse when devices
112
and
114
are packaged as four and eight-channel devices. When packaged in this way, devices
112
and
114
, when operating at a high chip-to-chip speed, i.e., 125 Mb/s, each require 80 pins and 160 pins to support four and eight-channel devices, respectively. Further, devices
112
and
114
, when operating at a slower chip-to-chip speed, i.e., 62.5 Mb/s, each require 160 pins and 320 pins to support four and eight-channel devices, respectively.
The pin problem reaches critical stages when devices
112
and
114
are scaled up to handle a 2.5 Gb/s data rate from the current 1.25 Gb/s data rate. At these higher speeds, devices
112
and
114
, when operating at a high chip-to-chip speed, i.e., 125 Mb/s, require 160 pins and 320 pins to support four and eight-channel devices, respectively. Further, devices
112
and
114
, when operating at a slower chip-to-chip speed, i.e., 62.5 Mb/s, require 320 pins and 640 pins to support four and eight-channel devices, respectively.
Thus, there is a great need to reduce the pin counts of devices
112
and
114
when devices
112
and
114
are scaled up to handle a 2.5 Gb/s data rate. (In addition to consuming huge amounts of silicon real estate, large pin count devices also consume large amounts of power.)
One conceptual approach to reducing the pin counts is to exchange data between devices
112
and
114
with a single-ended signal that has a lower maximum voltage. For example, by lowering the maximum voltage of a single-ended data signal from 3.3V to 500 mV, the frequency of the data signal can be increased from 125 Mb/s to approximately 1.25 Gb/s without exceeding the EMI requirements. By lowering the maximum voltage from 3.3V to 250 mV, the frequency of the data signal can be increased from 125 Mb/s to approximately 2.5 Gb/s without exceeding the EMI requirements.
One problem with this conceptual approach, however, is that it is extremely difficult, if not impossible, to form inbound detectors on processing device
114
, and outbound detectors on device
112
, that accurately detect logic ones and logic zeros from a single-ended gigahertz data signal that has a maximum voltage in the hundreds of millivolts due to the voltage margins required by the detectors.
Another problem with this conceptual approach is that much more complex clock recovery circuitry is required to recover a clock signal from a data signal operating in the gigahertz range, such as 2.5 GHz, than from a data signal operating in the megahertz range, such as 125 MHz. Thus, much of the clock recovery circuitry that is utilized in the serdes would also be required in processing device
114
to recover the clock from a gigahertz data signal (output by device
112
to device
114
) that has a maximum voltage in the hundreds of millivolts.
Another approach to reducing the pin count, that also avoids this duplication, is to integrate the functions of physical layer device
112
and processing device
114
on a single chip. One problem with this approach, however, is the incompatibility of high-precision analog circuits, which make up most of the circuits on physical layer device
112
, with digital circuits, which make up most of the circuits on processing device
114
.
One of these incompatibilities is the speed with which new processing technologies can be implemented. For the present, digital circuits are easily adapted to new (and smaller) processing technologies because the voltage levels that represent logic ones in the new processing technologies are still easily distinguished from the vo
Hunton & Williams LLP
Phu Phoung
Rambus Inc.
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