High-speed CMOS-to-ECL translator circuit

Details High-speed CMOS-to-ECL translator circuit High-speed CMOS-to-ECL translator circuit

1991-08-12

1992-07-21

Pascal, Robert J.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307446, 307448, 307455, H03K 1900

Patent

active

051325721

ABSTRACT:
A high-speed CMOS-to-ECL translator circuit for receiving CMOS complementary input signals and for converting the CMOS input signals to ECL differential output signals includes a differential pair of MOS input transistors (N4,N3), a constant current source (I.sub.s), a first output stage, and a second output stage. The first output stage is formed of a first MOS output transistor (N2) and a second MOS output transistor (P1). The second output stage is formed of a third MOS output transistor (N2) and a fourth MOS output transistor (P2). The gates of the first and second input transistors (N4, N3) are responsive to the CMOS complementary input signals (D, DB). The first output stage generates one of the ECL differential output signals (Q) at a first output terminal (18), and the second output stage generates the other one of the ECL differential output signals (QB) at a second output terminal (20). The translator circuit has an extremely short propagation delay time at its output terminals in response to input voltage changes applied to its input terminals.

REFERENCES:
patent: 4656375 (1987-04-01), Lauffer et al.
patent: 4704549 (1987-11-01), Sanwo et al.
patent: 4947061 (1990-08-01), Metz et al.
patent: 5036224 (1991-07-01), Wendell
patent: 5043604 (1991-08-01), Komaki
patent: 5047671 (1991-09-01), Suthar et al.
patent: 5084637 (1992-01-01), Gregor

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