High speed CMOS sense amplifier

Details High speed CMOS sense amplifier High speed CMOS sense amplifier

1980-08-18

1984-07-24

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307355, 307279, H03K 524, H03K 3356

Patent

active

044619650

ABSTRACT:
A pair of CMOS inverters are cross coupled in a latching configuration. Both inverter supply terminals are coupled to complementary toggles that can render the inverters operative or inoperative. First, the inverters are rendered inoperative. An output switch is coupled between the output nodes so that the inverter's output nodes can be driven to the same potential, thus canceling any offset voltage. An input switch produces sampling over a time interval that extends beyond the output switch on period. After the sampling period, the toggles are operated to turn the inverters on and to produce a latch state determined by the potential change present in the sampling interval.

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patent: 4191900 (1980-03-01), Redfern et al.
patent: 4198622 (1980-04-01), Connolly, Jr. et al.
patent: 4238841 (1980-12-01), Clemen et al.
patent: 4316105 (1982-02-01), Fowler
patent: 4317054 (1982-02-01), Caruso et al.

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