High speed CMOS output buffer circuit minimizes output signal os

Details High speed CMOS output buffer circuit minimizes output signal os High speed CMOS output buffer circuit minimizes output signal os

1992-06-12

1993-09-28

Hudspeth, David R.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307475, 307263, H03K 1900

Patent

active

052489060

ABSTRACT:
An output buffer circuit is disclosed that minimizes signal oscillation or ringing on a data bus while limiting the power dissipated. This circuit includes a pair of reference voltage generators which provide clamp voltages that limit the signal oscillation and a mechanism for shutting down the appropriate generator when it is not operating. The output buffer circuit has the capability of driving the output transistors to their CMOS levels in order to maximize the sinking and sourcing currents.

REFERENCES:
patent: 4622482 (1986-11-01), Gauger
patent: 4894561 (1990-01-01), Nogami
patent: 4972101 (1990-11-01), Pantovi et al.
patent: 4975598 (1990-12-01), Borkar
patent: 4975599 (1990-12-01), Petrovick, Jr. et al.
patent: 5017807 (1991-05-01), Kriz et al.

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