High speed CMOS multiplexer having reduced propagation delay

Details High speed CMOS multiplexer having reduced propagation delay High speed CMOS multiplexer having reduced propagation delay

1990-06-04

1991-04-30

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307243, 307451, 307584, 307585, G06F 314

Patent

active

050121260

ABSTRACT:
A CMOS multiplexing circuit is provided for selecting one of a plurality of input signals under control of a digital select signal for providing an output signal inverted with respect to the selected input signal. A plurality of processing channels one for each input signal and each having exactly first, second, third and fourth transistors serially connected between first and second sources of operating potential are repsonsive to the digital select signal whereby only the second and third transistors in the selected processing channels are enabled. The other processing channels supporting the remaining input signals are disabled. The first and fourth transistors of the selected processing channel are alternately enabled by one of the plurality of input signals for providing the inverse state thereof at the output formed at the interconnection of the second and third transistors. The first and second sources of operating potential need pass through only two transistors which improves the propagation delay and since only the second and third transistors of the selected processing channels are conducting, the transistors forming the remaining non-selected processing channels are effectively removed from the output terminal thereby reducing the capacitive load thereon and improving the propagation delay in the select path.

REFERENCES:
patent: 4019178 (1977-04-01), Hashimoto et al.
CMOS: Higher speeds, more drive and analog capability expand its horizons, Electronic Design 23, Nov. 8, 1978, David Bingham.
A COS/MOS Dual NAND Buffer Circuit, Blandford, Gimber, Electronics Industry, Jul. 1978.

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