High speed CMOS logic device for providing ECL compatible logic

Details High speed CMOS logic device for providing ECL compatible logic High speed CMOS logic device for providing ECL compatible logic

1990-01-26

1991-03-05

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307450, 307451, 307443, 307448, 307585, H03K 19092, H03K 19094, H03K 19017, H03K 1704

Patent

active

049980289

ABSTRACT:
CMOS ECL drive circuit for providing regulated ECL logic levels. A CMOS logic circuit is connected by parallel N channel and P channel devices to serially connected N and P channel devices. The serially connected N and P channel devices are connected across a CMOS power supply with gate connections connected to the logic circuit. The parallel devices provide a regulating feedback current to one of the serially connected P channel and N channel devices during each of first and second ECL logic states. The feedback current effectively controls the bias on the gate connections of the serially connected P and N channel devices. The voltage at the junction of the serially connected P and N channel devices is regulated by each of the parallel connected devices.

REFERENCES:
patent: 4797583 (1989-01-01), Ueno et al.
patent: 4806802 (1989-02-01), Okitaka et al.
patent: 4835419 (1989-05-01), Chappell et al.
patent: 4845381 (1989-07-01), Cuevas
patent: 4906871 (1990-03-01), Iida
patent: 4947061 (1990-08-01), Metz et al.

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