High speed CMOS driver circuit

Details High speed CMOS driver circuit High speed CMOS driver circuit

1990-09-04

1992-11-17

Sikes, William L.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307473, 307310, 3072722, 307491, H03K 301, H03K 3289

Patent

active

051650460

ABSTRACT:
A high-speed CMOS driver circuit which compensates for the intervening transmission line effects resulting from the existence of a printed circuit board, or a ceramic or silicon substrate between the coupled CMOS devices, thus preventing significant signal degradation. Several techniques are employed to increase circuit speed. Firstly, P-channel and N-channel output drivers are sized so that the characteristics impedance of each of the devices matches the characteristic impedance of its associated transmission line (whether it be on a printed circuit board or on a ceramic or silicon substrate). A printed circuit board transmission line may be of either the microstrip or stripline variety. Secondly, since P-channel and N-channel output drivers must be capable of delivering relatively high current, it is therefore highly desirable to eliminate or greatly reduce any crowbar current that could flow during the brief transition state when both N-channel and P-channel devices are on. Several preferred circuit designs are identified for the reduction or elimination of this crowbar current.

REFERENCES:
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patent: 4612466 (1986-09-01), Stewart
patent: 4707620 (1987-11-01), Sullivan et al.
patent: 4841170 (1989-06-01), Eccleston
patent: 4859877 (1989-08-01), Cooperman et al.
patent: 4952818 (1990-08-01), Erdelyi et al.
patent: 4980586 (1990-12-01), Sullivan et al.
patent: 5001369 (1991-03-01), Lee
patent: 5095231 (1992-03-01), Sartori et al.

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