High speed CMOS differential interface circuits

Details High speed CMOS differential interface circuits High speed CMOS differential interface circuits

1990-08-01

1992-04-14

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307494, 3072968, H03K 190175, H03K 301, G06K 712

Patent

active

051051079

ABSTRACT:
High speed CMOS differential input and output interface circuits comprise input and output means arranged to be controlled by biasing means. The biasing means generates a bias voltage. The output interface has a single ended to differential translator as the input means and an differential output stage as the output means. The input interface has a input amplifier and detector as the input means, and a differential to single ended level translator as the output means. The input and output interfaces operate at 300 MHz and 200 MHz respectively using clock encoded data, and both are capable of interfacing with bipolar devices. A combined input/output interface operates at 200 MHz using clock encoded data or 60 MHz under normal clocked operation.

REFERENCES:
patent: 4573212 (1986-06-01), Svager
patent: 4622480 (1986-11-01), Uchimura et al.
patent: 4645951 (1987-02-01), Uragami
patent: 4727265 (1988-02-01), Nanbu et al.
patent: 4779015 (1988-10-01), Erdelyi
patent: 4783604 (1988-11-01), Ueno
patent: 4808848 (1989-02-01), Miller
patent: 4945258 (1990-07-01), Picard et al.

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